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| The PSC9132 for picocells can support 64 users in a single 20MHz LTE sector, with 150 Mbps DL and 75 Mbps UL. |
At the 2011 Mobile World Congress in Barcelona, Freescale Semiconductor announced their planned introduction of a set of "base station on-a-chip" SoCs - the PSC9130/PSC9131 for femtocells, and the PSC9132 for picocell and enterprise-femtocell applications - with the goal of availability in the second half of this year. Today, at the company's Technology Forum in Shenzen - China, Freescale announced that they have working silicon and are now sampling the products to selected customers.
Stephen Turnbull, Division Marketing Manager for Freescale's Wireless Access Division, says that the PSC913X family is designed to be scalable from from small to large cells, by integrating multiple combinations of the StarCore SC3850 DSP and Power Architecture® e500 core, with the MAPLE-B2F Baseband Accelerator Engine. The PSC9130 integrates a single set of cores, which designers can operate at a 800MHz clock rate for residential femtocells that can support up to 8 users. The PSC9131 offers increased capacity with a 1GHz core clock rate, for small-business applications with up to 16 users. All processors in the family support simultaneous multimode operation and a range of air interfaces.
The PSC9130/9131 supports:
The PSC913X support LTE in both FDD (Frequency Division Duplex) and TDD (Time Division Duplex) systems, and provide an interface for the JESD 207 Baseband Digital Parallel (RBDP) standard, and 2X2 MIMO (multiple input multiple output) antennae interfaces. Turnbull says that the PSC913X eliminate the need for additional support chips such as FPGAs. The products also provide support for GPS synchronization and 2G/3G sniffing, the latter a key to enable the future implementation of SON (self-organizing networks).
The PSC9132 integrates a pair of e500and SC3850 cores with the MAPLE-B2P baseband accelerator. The devices can be operated with a 1GHz to 1.2GHz clock rate, to support up to 64 users for picocell/enterprise femto base station applications. The additional processing power in the PSC9132 can support a single 20 MHz sector of LTE with an increase in bandwidth to 150 Mbps DL and 75 Mbps UL. Antenna support is also increased to 2x4 MIMO. Freescale added a 4-lane SerDes (serializer-deserializer) to the PSC9132, combining 2x Ethernet SGMII (Serial Gigabit Media Independent Interface), 2x CPRI (Common Public Radio Interface) v4.1 with a 6.144G antenna interface, 1x PCIe (Peripheral Component Interconnect Express) at 5G x2 lanes, and a Quad JESD207 RF transceiver interface.
Freescale and its partners are providing a range of L1, L2, L3 and transport software that has been integrated and tested on PSC9130/1/2 platforms. Freescale-licensed software is available for LTE-FDD/TDD and WCDMA (HSPA+) applications. L2/L3 Software for LTE-FDD/TDD and WCDMA is licensed by Aricent and Continuous Computing/Radisys.Transport software is offered by Freescale through the company's VortiQa package.
Freescale is also offering development boards for the PSC9132 and the PSC9130/9131
PSC9132 Development System
PSC9131 Form Factor Reference Design Board
Availability
Freescale is currently sampling QorIQ Qonverge products to select customers.
Stephen Turnbull, Division Marketing Manager for Freescale's Wireless Access Division, says that the PSC913X family is designed to be scalable from from small to large cells, by integrating multiple combinations of the StarCore SC3850 DSP and Power Architecture® e500 core, with the MAPLE-B2F Baseband Accelerator Engine. The PSC9130 integrates a single set of cores, which designers can operate at a 800MHz clock rate for residential femtocells that can support up to 8 users. The PSC9131 offers increased capacity with a 1GHz core clock rate, for small-business applications with up to 16 users. All processors in the family support simultaneous multimode operation and a range of air interfaces.
The PSC9130/9131 supports:
- Single 20MHz sector LTE (Long-Term Evolution) Release 9 at up to 100Mbps (million bits per second) DL (download) and 50 Mbps UL (upload).
- WCDMA (Wideband Code Division Multiple Access) Release 99/7/8.
- HSPA+ (High Speed Packet Access) in a 5 MHz single sector at 42Mbps DL, 11 Mbps UL
The PSC913X support LTE in both FDD (Frequency Division Duplex) and TDD (Time Division Duplex) systems, and provide an interface for the JESD 207 Baseband Digital Parallel (RBDP) standard, and 2X2 MIMO (multiple input multiple output) antennae interfaces. Turnbull says that the PSC913X eliminate the need for additional support chips such as FPGAs. The products also provide support for GPS synchronization and 2G/3G sniffing, the latter a key to enable the future implementation of SON (self-organizing networks).
The PSC9132 integrates a pair of e500and SC3850 cores with the MAPLE-B2P baseband accelerator. The devices can be operated with a 1GHz to 1.2GHz clock rate, to support up to 64 users for picocell/enterprise femto base station applications. The additional processing power in the PSC9132 can support a single 20 MHz sector of LTE with an increase in bandwidth to 150 Mbps DL and 75 Mbps UL. Antenna support is also increased to 2x4 MIMO. Freescale added a 4-lane SerDes (serializer-deserializer) to the PSC9132, combining 2x Ethernet SGMII (Serial Gigabit Media Independent Interface), 2x CPRI (Common Public Radio Interface) v4.1 with a 6.144G antenna interface, 1x PCIe (Peripheral Component Interconnect Express) at 5G x2 lanes, and a Quad JESD207 RF transceiver interface.
Freescale and its partners are providing a range of L1, L2, L3 and transport software that has been integrated and tested on PSC9130/1/2 platforms. Freescale-licensed software is available for LTE-FDD/TDD and WCDMA (HSPA+) applications. L2/L3 Software for LTE-FDD/TDD and WCDMA is licensed by Aricent and Continuous Computing/Radisys.Transport software is offered by Freescale through the company's VortiQa package.
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| Freescale offers a complete communications platform development system for the PSC9132l |
PSC9132 Development System
- Complete communications platform enabling LTE, WCDMA/HSPA+ and WiMAX.
- Dual-band system covering up to 2.7 GHz.
- Integrated Local and RRH (Remote Radio Head ) RF interfaces.
- Development and debugging tools available from Freescale and partners.
- Integrated with Analog Devices RF solution.
PSC9131 Form Factor Reference Design Board
- Complete communications platform enabling CDMA-2000, LTE, WCDMA/HSPA+ and WiMAX.
- Dual-band system covering up to 2.7 GHz.
- Development and debugging tools available from Freescale and partners.
- Integrated with Maxim and Analog Devices RF solutions.
Availability
Freescale is currently sampling QorIQ Qonverge products to select customers.
Related Article:
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| Berkeley Design Automation and its EDA partners will hold a nanometer Circuit Verification Forum in Santa Clara on September 22. |
On September 22, immediately following the conclusion of the IEEE Custom Integrated Circuits Conference, BDA (Berkeley Design Automation) will be hosting a "nanometer Circuit Verification Forum" at the TechMart in Santa Clara, CA. In past years, the day after CICC had been reserved for the BMAS (Behavioral Modeling and Simulation) Conference, which ceased operation after the 2010 event.
Organizers of the nanometer Circuit Verification Forum:
- Berkeley Design Automation - provider of analog FastSPICE.
- Accelicon - provider of tools and services for device modeling, including MQA (Model Quality Assurance) and SPICE model generation software - MBP.
- Ciranova - maker of analog layout automation tools operating with the Open Access database, including Helix and PyCell Studio.
- MunEDA - developer of the Wicked circuit optimization tool.
- Invarian - suppler of the InVar tools for temperature-aware layout analysis.
- Solido - provider of tools for circuit variation analysis.
The agenda will include presentations and demonstrations for designers of applications such as data converters, PLLs, high-speed I/O, and image sensors. Registration is free at the nm-forum.com website.
Breaking news:
Tim Cook Named CEO and Jobs Elected Chairman of the Board
Just last week, the San Jose Mercury News reported that "Apple co-founder Steve Jobs' biography coming sooner than expected". The story was updated just yesterday (August 23) to say that the original story omitted the release date for Steve Jobs' biography. "It is scheduled for publication Nov. 21, instead of the original date of March 2012."
No doubt millions worldwide are now questioning the state of Steve Jobs' health once again. Hopefully, he simply decided to walk away at the top. However, the official letter published on the Apple web site calls that into question, with Jobs saying he can "no longer meet my duties.Apple on Thursday declined to comment and referred questions to Simon & Schuster. The publisher said simply that "the book was finished and deemed ready to publish." Ditto the author, best-selling biographer Walter Isaacson, who downplayed any suggestion that the moved-up date was connected in any way to Jobs' health or his battle with pancreatic cancer."It's actually not related to any decline," Isaacson wrote in an email to Fortune magazine this week. "I turned most of the book in this past June. It's now all done and edited. The March 2012 date (or whatever date it was) was never a deeply considered pub date. Like the original cover design, it came about because the publisher wanted to put something in the database last spring."
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| The Blue Gene/Q SoC integrates 18 homogenous cores in a 1.47 billion transistor, 45nm SOI-CMOS chip. |
At the Hot Chips Conference held at Stanford University last week, IBM design manager Ruud Haring presented details of the Blue Gene/Q project, an international collaborative effort between geographically dispersed teams of IBM engineers, Columbia University and the University of Edinburgh in Scotland. The primary objective of the project is to develop a system for massively parallel supercomputing that can be used for for large scale scientific and analytics applications, while also laying the groundwork for 'exascale' computing. Exascale refers to the target of achieving a 1000X increase in performance over today's fastest supercomputer. That designation currently belongs to the Tianhe-1A, which was built by Chinese researchers. The U.S. Department of Energy is leading an effort to maintain U.S. leadership in computing, and has contributed funding to the Blue Gene/Q project through the Argonne and Livermore national laboratories.
Haring provided a tour of the roughly 19mm X 19mm die, containing 1.47 billion transistors, which IBM has fabricated in a 45nm SOI (silicon on insulator) CMOS process. The die photo shown here was taken prior to deposition of metal layers. There are a total of 18 identical instances of IBM's A2 processor core, 16 for user applications, 1 for operating system services, and 1 "redundant" core as extra insurance against yield fallout in this complex SoC (system on chip). The processor core was described as being mostly the same as the PowerEN (Power Edge of Network) chip, which IBM presented at the 2010 ISSCC (International Solid State Circuits Conference). The cores run the 64-bit Power instruction set architecture, and are operated at 1.6GHz with a 0.8 volt supply, though the design is capable of operation at 2.4 GHz. The design team scaled back voltage and clock frequency in order to reduce active power consumption and leakage.
Supercomputers enable simulation - that is, the numerical computations to understand and predict the behavior of scientifically or technologically important systems - and therefore accelerate the pace of innovation. Simulation enables better and more rapid product design. Simulation has already allowed Cummins to build better diesel engines faster and less expensively, Goodyear to design safer tires much more quickly, Boeing to build more fuel-efficient aircraft, and Procter & Gamble to create better materials for home products. Simulation also accelerates the progress of technologies from laboratory to application. The United States must excel at such tasks to compete in a rapidly developing global economy. - DOE Undersecretary for Science Steven E. Koonin
Haring provided a tour of the roughly 19mm X 19mm die, containing 1.47 billion transistors, which IBM has fabricated in a 45nm SOI (silicon on insulator) CMOS process. The die photo shown here was taken prior to deposition of metal layers. There are a total of 18 identical instances of IBM's A2 processor core, 16 for user applications, 1 for operating system services, and 1 "redundant" core as extra insurance against yield fallout in this complex SoC (system on chip). The processor core was described as being mostly the same as the PowerEN (Power Edge of Network) chip, which IBM presented at the 2010 ISSCC (International Solid State Circuits Conference). The cores run the 64-bit Power instruction set architecture, and are operated at 1.6GHz with a 0.8 volt supply, though the design is capable of operation at 2.4 GHz. The design team scaled back voltage and clock frequency in order to reduce active power consumption and leakage.
Each processor core on the Blue Gene/Q has a dedicated quad FPU (floating point unit), a 4-wide double precision SIMD (single instruction multiple data) architecture which can support 8 concurrent operations. The processors share a central 32MB DRAM L2 cache, which is unique in supporting transactional memory, speculative execution, and atomic operations. The left and right sides of the SoC are dedicated to dual memory controllers that support 16 GB of external DDR3 memory at a 1.33 Gb/s data rate, configured in a 2x16 byte-wide interface + supplemental ECC (error-correcting code) bits.
Built-in chip-to-chip networking enables each Blue Gene/Q to communicate with 10 neighbors, through on-chip router logic that operates autonomously from the cores. Packets for complex floating point operations can flow through the network without disturbing the processor cores. A crossbar switch in the center of the die was manually layed out in order to optimize wiring. Peak performance for the chip was specified at 204.8 GFLOPS with 55w power dissipation.
The L2 cache provides the point of coherency between cores. Users can define the start and end of transactions in the L2 cache, and the cache is designed to guarantee "atomicity", which IBM said eliminates the need for locks. Load/store conflicts are automatically detected and reported, so that they can be resolved by software. Haring showed data that demonstrated how transactional memory with atomic operations reduced the number of L2-to-processor round trips, cutting CPU cycles for load/store operations from 14,000 cycles to less than 1000 cycles with atomic operation.
The Blue Gene/Q is designed so that the health of each processor core is accessed through a scan chain during manufacturing test. If a single core is bad, a logical to physical re-mapping is performed to shift the bad core to last ID in the 18-core sequence. Haring said that this approach was "totally inspired" by array redundancy. The benefit is increased yield and reduced TTM (time to market), since a perfect die with 1.47B transistors is not required. Redundancy can be invoked at any manufacturing test stage from wafer test, to module, card, or system. The redundancy information can be stored in the chips eFuses, or in EEPROM (electrically programmable read only memory) so that a defective core can be shut down at boot time. The operation is totally transparent to system software.
At assembly, the Blue Q and 16GB of DDR3 chips are solder-attached directly to the same card, electrically connected through the Blue Q's integrated DDR3 PHY (physical interface) I/O blocks. The compute cards can use either an air-cooled or water-cooled heat sink. A total of 32 cards, containing a 16-core processor each, constitute a 512 processor node card, which are then paired into a 1024 processor rack.
Design Challenges
Haran emphasized that minimizing power was the overarching challenge for the Blue Q design methodology. The team employed architecture and logic level clock gating, and tuned the processor cores for low power. Power-aware synthesis was used, and the physical design of the clock networks also placed an emphasis on power-efficiency. The processor cores originated in a high-speed custom design methodology, but the rest of the chip was implemented as an ASIC. The merging of custom and ASIC methodologies presented a challenge. Functional verification of the transactional memory was difficult, with extensive use of cycle simulation and hardware acceleration. The designers built a complete multi-FPGA prototype, which was a key to achieving first pass silicon success.
Finally, Haran said that he would like to speak with any EDA representatives in the audience, to find a way to parallelize the test pattern generation with full-chip models, which he said is a weeks-long bottleneck.
Related article:
Touchstone Semiconductor has announced that evaluation boards for the company's TS1001 operational amplifier and TS9001-1/TS9001-2 voltage monitor ICs - are available to potential customers at no charge until September 30.
Engineers can register for their free demo boards by providing a valid corporate email on the Touchstone website: http://www.touchstonesemi.com/freedemoboards.html.
TS1001 Low-Power Op Amp Demo Board
The TS1001 demo board provides both non-inverting and inverting configurations. Touchstone claims that the TS1001 single-supply op amp reduces power requirements by at least half compared to any other available amplifier. The TS1001 is specified to operate on a 0.8V supply while consuming less than 0.6µA supply current.
TS9001 Low-Power Voltage Monitor Demo Board
The TS9001 demo board contains the push-pull TS9001-1 and the open-drain TS9001-2. Touchstone has configured each circuit as a simple threshold detector with additional hysteresis. The TS9001-1 and the TS9001-2 voltage monitor ICs incorporate a +1.252V reference with a 1% initial accuracy. The TS9001-1 offers a push-pull output stage with increased output current drive while the TS9001-2 offers an open-drain output stage that can be used in mixed-voltage systems design. Both TS9001s are specified to operate from +1.6V to 5.5V supplies while consuming less than 0.65µA supply current.
As you most likely know, on August 18th HP announced that they would stop producing devices based on the webOS, which they acquired by purchasing Palm for $1.2 billion little more than one year ago:
HP will discontinue operations for webOS devices, specifically the TouchPad and webOS phones. The devices have not met internal milestones and financial targets. HP will continue to explore options to optimize the value of webOS software going forward.
What a difference a year makes! From the beginning, one of the fundamental problems with the Palm acquisition has been the lack of an ecosystem and no significant traction with app developers. It appears that HP is still confused about this critical aspect of building a mobile OS ecosystem, and they are sending mixed messages now that certainly won't make it any better.
In their press release yesterday HP said they would "continue to explore options" regarding the webOS software, but in the message below - which the company sent to webOS developers today - HP states they will "continue to support, innovate, and develop the webOS App Catalog".
In their press release yesterday HP said they would "continue to explore options" regarding the webOS software, but in the message below - which the company sent to webOS developers today - HP states they will "continue to support, innovate, and develop the webOS App Catalog".
OK HP, which is it?
- In "Practical power gating and dynamic voltage/frequency scaling issues", AMD fellow Stephen Kosonocky reviewed the tradeoffs that the company's engineers had to consider in the design of the Llano APU (accelerated processing unit). It was clear that, in optimizing their design, the AMD engineers performed a thorough analysis in considering all the potential issues, such as EM (electro-migration), surge currents, IR drop, etc. Kosonocky showed that chip-package co-design is mandatory as the package constraints, due to the cost of adding power planes and routing congestion, limit how much designers can optimize and segregate power-performance across an SoC. The AMD presentation provided the setup for the talks that followed, showing that the ability to add more cores to an SoC will be limited by the degrees of freedom engineers have to tune the voltage for various portions of a chip. This need drives the requirement for integrating voltage regulators on-chip.
- In "Integrated Inductors with Magnetic Materials for On-Chip Power Conversion", Don Gardner - of Intel's Labs for Circuit Research and Future Technology, shared results of their work on adding magnetic materials to a standard CMOS process. Gardner showed detailed information on the work that he and his colleagues have conducted to build on-chip buck converters with coupled inductors. The high inductance density that is needed led to evaluation of materials such as CoZrTa (cobalt, zirconium, tantalum) and NiFe (nickel-iron) metallization. It was fascinating to see the analysis of "magnetic vias", analogous to conventional signal and power vias, but with the purpose of efficiently coupling flux in what is in essence an on-chip transformer with magnetic windings around a core.
- The last presentation in the session was by Profesor Elad Alon, of UC Berkeley and the Berkeley Wireless Research Center. In "Fully Integrated Switched-Capacitor DC-DC Conversion", Alon described a somewhat more conventional approach, using capacitors rather than inductors, to build on-chip DC-DC converters. This could offer an advantage by not requiring addition of any high-cost processing steps in device fabrication. Intel was, understandably, not able to speak on the costs of adding magnetic materials to perform the same function. Anon also projected the use of switched capacitor voltage regulators in stacked-die 2.5D/3D configurations, where an older, lower-cost technology could be used to supply power distributed across the surface of a more advanced multi-core processor SoC.
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| Google to Acquire Motorola Mobility, says "Combination will Supercharge Android". |
As anyone connected to the internet must know by now, Google's announcement of its intent to purchase Motorola Mobility disrupted a normally quiet summer Monday morning like one of the solar flairs that threaten to wreak havoc on all earthly electronic communications. The company made the announcement in a conference call at 5:30 AM Pacific time, clearly a violation of the company's "do no evil" philosophy!
Many commentators see the acquisition primarily as a strategic defense move in the escalating patent wars that are being waged by Microsoft, Apple, and Oracle. While saying that the acquisition will "supercharge Android" by accelerating innovation, Google CEO Larry Page also highlighted the value of Motorola's patents in his blog post:
We recently explained how companies including Microsoft and Apple are banding together in anti-competitive patent attacks on Android. The U.S. Department of Justice had to intervene in the results of one recent patent auction to “protect competition and innovation in the open source software community” and it is currently looking into the results of the Nortel auction. Our acquisition of Motorola will increase competition by strengthening Google’s patent portfolio, which will enable us to better protect Android from anti-competitive threats from Microsoft, Apple and other companies.
While there's no doubt that possession of the Motorola patents will provide Google with more ammunition with which to fight the "Rockstar Bidco” group in the short term, concluding that is all there is to it would be a mistake. Google's culture of innovation is well known. To continue to compete with Apple in the long term, Google will need to develop better, innovative "whole product solutions".
As Dr. Joel West (formerly of the San Jose State Lucas School of Business) describes it in his paper "How Open is Open Enough? Melding Proprietary and Open Source Platform Strategies",
This is the approach that Google took in founding the Open Handset Alliance, leaving it up to third parties to provide the hardware that drove Android to the top position in smartphone operating systems. But, that strategy has also led to fragmentation. While VP of Engineering Andy Rubin has defended Android's openness, the company has also found it necessary to switch preferred partners at seemingly every point of major innovation: with HTC for the first G1 and Nexus One, with Motorola for the first DROID, Honeycomb and the Xoom tablet, and with Samsung for the Nexus S. Bringing Motorola Mobility into Google eliminates the inefficiencies inherent in switching lead horses at every turn, and positions the company to better compete with Apple, which has progressively moved further into controlling their hardware from silicon on up. Meanwhile, the likes of HTC and Samsung can continue to compete and grow the ecosystem - to the degree that Android stays open.As Dr. Joel West (formerly of the San Jose State Lucas School of Business) describes it in his paper "How Open is Open Enough? Melding Proprietary and Open Source Platform Strategies",
Thus, to make a successful “whole product” solution, the owner of the innovation seeks to attract such complementary assets, in part by sharing the overall returns of the innovation with the third party supplier of such assets.
The lack of a whole product solution has been most evident in the Android-based Google TV strategy. The company's strategy of partnering with Intel, Logitech and Sony left Google TV shut out of the cable TV market. Motorola Mobility brings a leading provider of set top boxes to Google, a key missing ingredient. However, content is king in the TV business, just like apps in the smartphone business. To complete the TV picture, look for the bidding competition for Hulu to heat up between Apple and Google.
Related articles:
- Market analysts at Canalys increase Android market share to 48%
- Android's lead over iOS. Whose numbers should you believe?
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| TI claims that the TRF7970A NFC transceiver provides up to 2 times the battery life of competitive products |
Texas Instruments has announced availability of the new TRF7970A NFC (near-field communications) transceiver, which they claim offers the industry’s lowest power, extending battery life "up to 2 times longer than competitive products" by virtue of eight selectable power modes. TI is also offering royalty-free software stacks for the TRF7970A to developers, which they say are compatible across a broad range of the company's MSP microcontrollers.
Other features of the TRF7970A NFC platform:
Pricing and availability
TI’s new TRF7970A NFC development kit is immediately available for order at www.ti.com/nfc-pr-es for USD $99.
Other features of the TRF7970A NFC platform:
- Power modes range from 1 µA to 120 mA.
- Supports peer-to-peer communication, reader/writer capability and card emulation.
- Supports two crystal oscillator frequencies: 13.56MHz or 27.12MHz frequencies give engineers more flexibility in speed and cost options for their designs.
- 128 byte FIFO buffer for NFC communications allows developers using microcontrollers with low MHz to create products capable of handling large data transfers.
- Compliance with ISO/IEC 18092 and ISO/IEC 21481 standards gives developers the ability to create globally interoperable products.
- NFC Peer-to-Peer Initiator as well as Active and Passive Target Operation are available for MSP430™ microcontrollers.
- Supports multiple reader/writer protocols and includes demo software stacks for reader/writer mode ISO/IEC 15693, ISO/IEC 18000-3, ISO/IEC 14443A/B and FeliCa.
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| NXP Semiconductor has collaborated with Google to develop Google Wallet, a system for mobile payments that will launch in the U.S. with the Samsung Nexus-S smartphone on Sprint. (source "What is NFC and why it is a hot technology", IEEE Santa Clara Valley CES) |
Pricing and availability
TI’s new TRF7970A NFC development kit is immediately available for order at www.ti.com/nfc-pr-es for USD $99.
Related article:
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| Apache Design Solutions is now a wholly owned subsidiary of ANSYS |
Rather than quickly passing over the obligatory opening slide, Andrew Yang stops and points while reading the text that encapsulates the central purpose for our meeting - "Apache Design Solutions, a wholly -owned subsidiary of ANSYS, Inc." On August 1, ANSYS announced that they had successfully closed their purchase of Apache, for approximately $314 million in cash. The wholly-owned subsidiary designation is key. Dr. Yang will continue to carry the title of President of Apache Design Inc., while also assuming the role of Vice President and General Manager - as a member of ANSYS' senior management team. ANSYS is intent upon keeping Apache intact post-acquisition, with a total of $25M in payments and incentives that will be doled out to Dr. Yang, his staff and employees on the next three anniversaries through 2014.
With the acquisition now complete, taking just 7 weeks says Dr. Yang (but only 1 month after the June 30 announcement), he wants to address two questions that he has heard repeatedly: "Why no IPO?", and "Why ANSYS?" On the first question, the current condition of the stock market probably provides all the reason one needs for avoiding an IPO. But, if that were not enough, Yukari Ohno - Senior Director of Marketing, correctly points out that IPOs are a lot of trouble. Beyond market volatility, the additional work for regulatory filings, Sarbanes-Oxley, etc. make IPOs much less attractive than those who have already forgotten (or never knew) the dot-com bubble may think.
On the second question, Dr. Yang first points out that ANSYS is very experienced in M&A (mergers and acquisitions), and has been successful in two other large acquisitions: Ansoft in 2008, and Fluent in 2006. Furthermore, the company has been in business since 1970, and has (an astounding by EDA standards) 40,000 customers across industries that include aerospace and defense, robotics, industrial, energy, and automotive segments. The acquisition extends the ANSYS portfolio of tools to the chip level, where semiconductors are obviously critical to electronics system realization, with the goal being "chip aware system-level engineering simulation". In the process, Apache gains access to a much larger customer base and sales channel.
When they were promoting Apache for a potential IPO, the company vision that was presented to investors consisted of a set of solutions that spanned chips to packages to PCBs (printed circuit boards). This was a path that Apache was already on, starting with the acquisition of Optimal for package and board analysis in 2007, and continuing up to the RTL (register-transfer) level with the Sequence acquisition in 2009. Becoming a subsidiary of ANSYS will accelerate the vision of moving Apache up to system-level design, says Dr. Yang.
Now, the vision is that the combination of Apache and ANSYS will enable the combined companies to develop a unified solution to address signal integrity and power integrity, from chip to package to board. Signal integrity and noise issues, that may start with capacitive C(dv/dt) switching noise effects at the chip level, couple to inductive L(di/dt) effects in a package, and result in EMI (electro-magnetic interference) on a board. ESD (electro-static discharge) is also as serious on a board design as it is on a chip. ANSYS plans to integrate the Apache tools into a consistent workflow with their Workbench Platform, as they had previously done with the Ansoft tools.
With smartphones and mobile devices now driving the electronics industry, more analysis and optimization is required, which Apache-ANSYS describes as simulation-driven product realization. The challenges of 3D IC development will also be a focus, calling for co-simulation across component levels, including thermal analysis that ANSYS provides and which Apache had previously attempted to develop on their own.
To connect the chip to higher levels of system simulation, Apache will leverage their expertise in creating compact abstracted models, such as the CPM (Chip Power Model), and the CSM (Chip Signal Model) for DDR (double data rate) memories. This will be the key to enable handoff from Apache tools to the Ansoft/ANSYS 3D finite-element analyses. Apache will retain their 100% time-base licensing business model, adding a stream of revenue predictability to ANSYS' sales that continue to contain a mix of perpetual licenses.
As Dr. Yang sees it, regardless of the industry, success requires a combination of delivering customers value through a continual process of innovation, and the must-have of a sustainable (i.e. profitable) business model. As his earlier successes with Anagram, CADMOS, InnoLogic Systems, Ultima Interconnect Technology, and Mojave show, Dr. Yang has a knack for executing on that formula that few (if any) EDA executives can match.
Related articles:
Is HTML-5 the next trend for development of mobile applications? That is the topic that the Silicon Valley chapter of the Mobile Monday organization will discuss this evening, in a panel discussion at the Computer History Museum in Mountain View, CA.
The session will be moderated by Matt Asay - Senior Vice President, Business Development at Strobe Inc., developer of a web application development platform that seeks to make apps portable across any device.
Presenters:
- Daniel Zucker - Research Team Leader - Nokia
- Craig Walker - Chief Technology Officer of Xero, maker of online accounting software.
- Roderic March - CEO of Nanocrowd, a startup that is developing a movie search engine for iPads.
- Brian Fling - Director - mobile app developer Pinchzoom.
- Tiffany Brown - Web Evangelist at Norwegian web browser developer Opera.
- Niels Boegholm - VP Products at mobile social gaming company MocoSpace.
Related articles:
Mobile Monday - Silicon Valley: Year in Review and 2011 Predictions
Mobile Monday - Silicon Valley: Year in Review and 2011 Predictions
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| The Huwei Vision will feature a 3D carousel UI that enables users to quickly select the panel of apps they wish to use |
Although we are yet to see availability in the U.S. market, Huawei has continued to announce a series of devices that demonstrate their own unique take on the Android operating system. In June, the company announced a new 7" Android tablet, the Huawei MediaPad, which they claimed to be the first 7" tablet to run the Android 3.2 Honeycomb operating system, while the 10.1" Samsung Galaxy tablet and Motorola Xoom were still running Honeycomb version 3.1.
With their latest device - the Huawei Vision, which the company announced this week, Huawei is introducing a smartphone with a 3D user interface and carousel animation. The Vision displays 3D panels on the home screen, which allow users to quickly select any panel, similar to the 2D HTC Sense UI, or the Cooliris desktop application. The Huawei Vision will be introduced with the Android Gingerbread 2.3 OS running on a 1GHz Qualcomm Snapdragon MSM 8255 application processor.
Little information was provided by Huawei regarding release date or carriers, other than "available in selected markets from September". The Vision works in triband GSM and WCDMA/HSDPA/ HSUPA. Huawei will be seeking to leverage the popularity of the Angry Birds game, which they will be pre-installing along with Asphalt 6: Adrenaline, Order&Chaos Online and Guerrilla Bob HD.
Here are the limited details that were provided on the Huawei Vision smartphone
Technical Specs
- Unibody design
- Android Gingerbread 2.3 OS
- 3.7 inch capacitive multi-touch screen
- Measures 9.9mm (0.39 inches) at its thinnest point and weighs around 121g (0.27 pounds)
- 5M pixels auto focus camera with LED flash and video recording to 720P
- WiFi 802.11b/g/n and Bluetooth V2.1 with A2DP
- 1GHz Qualcomm Snapdragon MSM 8255 processor
- 1400mAH battery
- 512M RAM + 2G ROM memory with a memory card slot up to 32GB
- Micro USB 2.0 port
Additional Features
- Assisted GPS support
- FM radio
- Full range of messaging including SMS, MMS, Email, Push Mail and IM
- G-sensor, proximity sensor and light sensor
- Back covers available in silver, rose gold, and charcoal.
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| Inventors from Rearden Labs claim to have invented a "new kind of wireless network" that deliberately creates interference in order to increase capacity and speed of wireless networks. |
According to the Mercury News, Perlman claims that his technology, which he calls DIDO (Distributed-Input-Distributed Output), can increase wireless data throughput by embracing interference.
At first glance, there would seem to be a number of obvious DIDO RAN (radio access network) architectural similarities to current 4G techniques: MIMO (multiple input multiple output), pico/femto cells, and cloud-based RAN to name a few. A key to the DIDO system is to use the cloud, or a remote signal processing data center, to tune the signals that each radio head transmits based on the location and number of other DIDO transmitters in a particular area. By doing so, according to the Technology Review article, Perlman claims to have come up with a "new kind of wireless network" with thousands of times the capacity of a conventional network. By combining signals from multiple transmitters, the DIDO technique is claimed to be capable of creating "a bubble of crystal-clear reception around every user". The Technology Review did point out one possible downside - DIDO doesn't work for upload.(DIDO) uses multiple transmitters to create unique interference patterns at particular points in space that essentially become unique channels to which one or more devices can connect.
How creating separate, apparently localized, channels in this manner could increase the capacity of available spectrum is (no pun intended) unclear. Support for non-stationary receivers would also appear to be a huge issue. The technique also requires dedicated private spectrum, so it can't be used to fix congestion in WiFi hotspots. It would appear that the invention actually needs to avoid interference that is not of its own making, not exactly a viable real-world proposition.
While the Mercury News claimed that Perlman has released few of the technical details, so that it is difficult for experts to assess the credibility of the invention and his claims, there is actually a wealth of information that is freely available. Perlman and his colleagues have been granted a total of 4 U.S. patents:
| 7636381 | System and method for distributed input-distributed output wireless communications A system for dynamically adapting the communication characteristics of a multiple antenna system (MAS) with multi-user (MU) transmissions (defined with the acronym MU-MAS), such as a... | ||
| 7633994 | System and method for distributed input-distributed output wireless communications A system for compensating for in-phase and quadrature (I/Q) imbalances for multiple antenna systems (MAS) with multi-user (MU) transmissions (defined with the acronym MU-MAS), such as... | ||
| 7711030 | System and method for spatial-multiplexed tropospheric scatter communications A method is described comprising: transmitting a training signal from each antenna of a base station to each of a plurality of client devices utilizing tropospheric scatter, each of the client... | ||
| 7599420 | System and method for distributed input distributed output wireless communications A system and method are described for compensating for frequency and phase offsets in a multiple antenna system (MAS) with multi-user (MU) transmissions (“MU-MAS”). For example, a method... |
Though the association with a gaming site, where Perlman is CEO, is puzzling for an invention requiring expertise in radio engineering and DSP (digital signal processing), the list of inventors in the DIDO patents includes two wireless engineers with backgrounds that include Freescale Semiconductor and Samsung, according to LinkedIn.The other two co-inventors are OnLive employees.
A search at www.freepatentsonline.com found that the Rearden team also has 13 patent applications pending. Experts in wireless system design are invited to review the technical details behind DIDO, and share your opinions and comments with the EE Daily News.
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- Will 4G wireless networks move basestations to the cloud?
- Mindspeed: 5G networks will be enabled by software-defined cognitive radios
- Texas Instruments adds basestation SoCs for small cells
- Cavium MIPS64-based multicore processors for 4G applications
- DesignArt Networks releases LTE small cell base station reference designs
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| Gartner's 2010 Embedded MPU ranking for the ($776M) wired communications segment shows Freescale growing its #1 position over Intel |
Freescale Semiconductor recently announced results of a study of embedded MPU (microprocessor) market share rankings, conducted by the Gartner Group, which showed the company extending its lead in the wired and wireless networking segments. (Source: Gartner, Inc., “Market Share: Semiconductor Applications, Worldwide 2010”, Gerald Van Hoy et al, March 30, 2011.)
According to Mushell, while companies like NetLogic and Cavium are growing, in the communication processor market "too much emphasis has been placed on the smaller companies and niche applications". He points out that it is important to keep in mind the different requirements of control plane and data plane functions. Freescale has an advantage over competitors, says Mushell, with a deep understanding of the software required to efficiently handle packets of data. He notes that this is an advantage that goes back to the company's origins in Motorola.
“Adoption of multicore QorIQ processors among customers targeting wired and wireless communications processors is strong and getting stronger,” said Brett Butler, vice president and general manager of Freescale’s Networking Processor Division.The EE Daily News interviewed Sergis Mushell, Principal Research Analyst at Gartner for CPU, GPU, and storage semiconductors, to gain further insight into the study and the communications processor market in general.
According to Mushell, while companies like NetLogic and Cavium are growing, in the communication processor market "too much emphasis has been placed on the smaller companies and niche applications". He points out that it is important to keep in mind the different requirements of control plane and data plane functions. Freescale has an advantage over competitors, says Mushell, with a deep understanding of the software required to efficiently handle packets of data. He notes that this is an advantage that goes back to the company's origins in Motorola.
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| In the ($498M) wireless communications processor market, Freescale dominates with a 72.3% share, while NetLogic rose to 2nd place in 2010 with a 9.2% share. |
Scale is a critical attribute for a communications processor vendor, and Mushell says that Freescale is the "only one that qualifies" with the medium scale that is best suited for this market. ASICs are getting too expensive for smaller companies to produce, while a company with the size of Intel is too large to be interested in customizing devices with the I/Os that are required in different networking applications, he says. Freescale, on the other hand, is of a size where they are open to design ASICs to meet communication processor market requirements. Mushell advises though, to keep an eye on Intel in the storage market, where their ability to integrate many cores can be an advantage.
According to Gartner's analysis, the consumer segment for embedded MPUs shrunk in 2010, from $504M to $425M. Freescale was able to grow their share in this segment to 65.2% ($277M), while U.S. competitors Intel, Netlogic, and IBM each experienced declines. It is interesting to note the ascension of Chinese vendor Shenzen, who grew 50% while rising from 10th to 8th position in consumer applications of embedded MPUs.
Freescale gives an advanced look at 28nm, 64-bit multicore QorIQ design
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| In the consumer segment, Freescale grew their share to 65.2%, while Intel rose to 2nd place despite a decline to 11.5% |
Related articles:
Cavium MIPS64-based multicore processors for 4G applicationsFreescale gives an advanced look at 28nm, 64-bit multicore QorIQ design
Market analysts at research firm Canalys, in their Q2 2011 estimate of smart phone market shipments, have projected that devices based on the Android operating system continue to be the strongest growth driver in the smartphone market, with shipments of 51.9 million units. Canalys estimates a global market share of 48% for Android shipments in Q2. This represents a higher share for Android than the 38.9% 2011 share estimate of research firm IDC, that was matched by the Nielsen polling company's 39% Android share estimate for the U.S. market.
Canalys found that Android is strongest in the Asia Pacific region, with 39.8 million units shipped, compared to 35.0 million in EMEA (Europe, Middle East and Africa), and 32.9 million in the Americas. Android dominates in South Korea (home of Samsung), with an 85% platform share, and in Taiwan (home of HTC) with 71%. While Samsung has moved ahead of Nokia for the global lead in smartphones, Canalys's opinion is that this performance was underwhelming given the ongoing weakness of Nokia during its transition to Microsoft's Windows Phone 7 operating system. However, Canalys also noted that Samsung achieved year-on-year growth of 421%, not exactly poor results, which included 355% growth in devices carrying the entry-level smartphone operating system 'bada'. Bada is actually better positioned to take share from Nokia's Symbian, in the less developed markets where Nokia retains some strength, than is the more fully featured Android.
Nokia’s leadership position has proved most resilient in key emerging markets, and it still leads in the BRIC countries: Brazil, Russia, India and China. ‘The problem for Nokia is that demand for its Symbian-based smart phones has dissipated very rapidly, particularly in operator-led markets, such as Western Europe, where it’s been strong in the past,’ said Canalys Principal Analyst Pete Cunningham.
Canalys pegged Apple's shipments of 20.3 million iPhones in Q2 as equivalent to a global market share of 19%, just slightly higher than IDC's 2011 estimate of 18.2% for iOS. The firm put RIM at just 12% for the quarter, down from 33% a year ago and less than IDC's 2011 estimate of 14.2%, though the company's global shipments actually grew 11% year on year.
Android vs. MeeGo: two approaches to competitively leveraging "open source"
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Android's lead over iOS. Whose numbers should you believe? Android vs. MeeGo: two approaches to competitively leveraging "open source"
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| National Semiconductor has announced 7 new sensor AFEs, in 24-bit and 16-bit configurations. |
National Semiconductor Corp. has announced the availability of seven new 24-bit and 16-bit multi-channel sensor AFEs (analog front-ends). National has designed the LMP900xx series sensor AFEs to enable designers to easilly configure signal paths from interface sensors to microcontrollers. You can use the AFEs for precision sensing systems to monitor and control temperature, pressure, load, force, motion/position and voltage in industrial, medical, and test and measurement applications.
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Designers can use National's WEBENCH software to easily develop designs with the LMP900xx series sensor AFEs |
To ease the design process, National has developed the WEBENCH® Sensor AFE Designer software tool and bench-top development system. Designers can use WEBENCH to model attaching a sensor and configuration of the signal path, optimize their design, and download the configuration data for the sensor AFE for immediate prototyping. National has developed WEBENCH design kits for engineers to use with a variety of the company's products, and the WEBENCH FPGA Power Architect won EDN Magazine's Innovation Award in the Software Category earlier this year.
The LMP900xx is a pin-compatible family of products that include either a 24-bit or 16-bit sigma-delta ADC, with a programmable input MUX (multiplexer) that designers can use to interface up to 4-differential inputs, or seven single-ended inputs in any combination of input types. You can utilize the microcontroller interface by connecting through a standard 4-wire SPI (serial peripheral interface) which also provides CRC (cyclic redundancy check) data link error correction. Seven general purpose I/O ports are also available, and each IC is guaranteed over the -40 degrees C to 125 degrees C temperature range.
The LMP900xx IC’s incorporate background calibration at all gain setting (1, 2, 4, 8, 16, 32, 64 and 128) to eliminate offset and gain drift over time and temperature without disturbing the measured signal. You can configure each channel independently for gain and sample rate, with automatic, manual and single scan of selected channels. Continuous background sensor diagnostics are also provided for detecting shorts, opens and out-of-range signals.
The LMP90099/98/97 24-bit multi-channel, sensor AFEs provide various channel configurations and are supplied with or without matched current sources:
- The LMP90099 provides 24-bit resolution, 4-differential and 7-single-ended inputs without current sources.
- The LMP90098 provides 24-bit resolution, 2-differential and 4-single-ended inputs with two matched current sources.
- The LMP90097 provides 24-bit resolution, 2-differential and 4-single-ended inputs without current sources.
The LMP90080/79/78/77 16-bit multi-channel, sensor AFEs provide various channel configurations and are supplied with or without matched current sources:
- The LMP90080 provides 16-bit resolution, 4-differential and 7-single-ended inputs with two matched current sources.
- The LMP90079 provides 16-bit resolution, 4-differential and 7-single-ended inputs without current sources.
- The LMP90078 provides 16-bit resolution, 2-differential and 4-single-ended inputs with two matched current sources.
- The LMP90077 provides 16-bit resolution, 2-differential and 4-single-ended inputs without current sources.
More information about National’s sensor AFEs, WEBENCH Sensor AFE Designer and development system is available at http://www.national.com/sensorAFE.
Pricing and Availability
Offered in 28-pin TSSOP packages, National’s LMP900xx sensor AFE ICs are available now and range in cost from $3.25 to $4.95 in 1,000-unit quantities. For more information on the LMP90099/98/97 24-bit sensor AFEs or to order samples and an evaluation board, visit http://www.national.com/pf/LM/LMP90100.html. For more information on the LMP90080/79/78/77 16-bit sensor AFEs or to order samples and an evaluation board, visit http://www.national.com/pf/LM/LMP90080.html.
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| The GateRocket homepage notifies visitors that the company has ceased operations. |
GateRocket's first product, RocketDrive, was introduced in 2007. RocketDrive accelerated simulation for FPGA design verification by combining hardware and software for "Device Native verification". Designers could place portions of their design onto an FPGA in the RocketDrive, to speed up analysis over standard software simulation alone.The GateRocket technology immediately earned industry recognition, including 2007 top product awards from EDN and Electronic Design magazine.
GateRocket followed with RocketVision, a debug and visualization environment to go with RocketDrive that enabled simulators to have full visibility into the FPGA hardware. RocketVision helped designers to determine differences between design intent and FPGA behavior, by automatically inserting test points at any level of the design hierarchy and without requiring additional test pins on the FPGA's I/O.
In 2010 GateRocket introduced SoftPatch as a new feature in the RocketVision FPGA debug platform. SoftPatch enabled engineers to patch their FPGA designs with edited RTL (register-transfer level) software blocks, and evaluate the changes with RocketVision before re-running synthesis and place-and-route. With SoftPatch users would simulate the change in standard HDL software while the unchanged portion of the design executed in the native FPGA hardware in the RocketDrive.SoftPatch also earned industry awards, including the DesignVision award for IC Design Tools at the 2011 DesignCon, and nomination for the 2010 EDN Magazine Innovation Award in the EDA tools category.
There is no word yet regarding an acquisition of GateRocket's assets, but the tools could be valuable to both Xilinx and Altera should they be interested in picking them up. A form on the GateRocket home page invites visitors to submit questions and comments, and "someone will get back to you".
