Monday, June 20, 2011

Texas Instruments adds basestation SoCs for small cells

Texas Instruments has announced the TMS320TCI6612 and TMS320TCI6614 SoCs (System-on-Chips), at the Femtocell World Summit in London. The devices represent extensions of the company's KeyStone multicore architecture for developers of metro, pico and enterprise small cell base stations. TI previously announced the TCI6618,  for the high-end-base-station market in macrocell and compact-macrocell applications, at the 2011 MWC (Mobile World Congress) in February.

TI has integrated a mix of processing elements into the new devices, including radio accelerators, network and security coprocessors, combined fixed-and floating-point DSPs (digital signal processors) and an ARM® RISC processor.

TI's small-cell SoCs integrate an ARM Cortex-A8 processor with dual or quad DSP cores.

The integration of an ARM Cortex-A8 core is new with the TMS320TCI6612 (dual-core DSP) and TMS320TCI6614 (quad-core DSP). The TCI6618 also integrates a network coprocessor with DSP cores and other acceleration for layers 1 and 2 processing, which TI had previously said eliminates the need for a RISC processor.  TI provided further information to the EE Daily News with today's announcement, to clarify the differences in the small and large-cell SoC architectures.
For small cells, typically one sector solutions, it is the goal to have all the digital processing on a single device, hence this small SoC which includes the ARM for layer 3 processing.  In macro solutions (multiple sectors) several devices are often used together (for example 6616 or 18) for the layer 1 and 2 processing, while separate RISC based processor (for example an external ARM) interfaces to them for layer 3.
TI says that the integration of the ARM RISC core, with packet and security processors, greatly reduces small-cell base station system cost by providing a complete solution for layers 1, 2 and 3 and transport processing for high performance small cell base stations.

Embedded Layer-1 coprocessors/accelerators in the TMS320TCI6612 and TMS320TCI6614 include:
  • 4 enhanced Viterbi decoders.
  • 3 third-generation turbo decoder coprocessors.
  • A turbo encoder coprocessor.
  • 3 FFT (fast Fourier transform) coprocessors.
  • TFCI (transport format control identifier) , CQI (channel quality indicator)
  • 4  RSAs (rake/search accelerators) for CDMA (code division multiple access) assistance with chip-rate processing.
  • The BCP (bit-rate coprocessor) contains the modulator, demodulator, interleaver/de-interleaver, turbo and convolution encoding, rate matcher/rate de-matcher, correlator for block code decoding, and CRC
    engine. The BCP enables turbo interference cancellation for MIMO (multiple-input, multiple-output) equalization and enables high-performance PUCCH (Physical Uplink Control Channel) format 2 decoding. According to TI, the BCP offloads approximately 15 GHz of CPU MIPS.
Layer-2 accelerators include:
  • ROHC (Robust Header Compression).
  •  QoS (Quality of Service).
  • RLC/MAC (Radio Link Control and Medium Access Control).
 The TCI6612 and TCI6614 I/O (input/output) support includes:
  • I2C (inter-IC), SPI (serial peripheral interface), and UART (universal asynchronous receiver/transmitter).
  • PCI Express port with two lanes supporting GEN1 and GEN2.
  • Twelve 64-bit general-purpose timers (also configurable as sixteen 32-bit timers).
  • 32-pin GPIO (general-purpose input/output) port with programmable interrupt/event generation mode.
  • Four lanes of SRIO (serial RapidIO), compliant with RapidIO 2.1 for up to 5-Gbps operation per lane.
  • 1.6 GHz, 64-bit DDR3 SDRAM (double data rate, synchronous dynamic random access memory) interface, supports up to 8GB of addressable memory space.
  • 16-bit EMIF (external memory interface) for connecting to flash memory (NAND and NOR) and asynchronous SRAM (static RAM).
  • Second-generation SERDES-based AIF2 (antenna interface) capable of up to 6.144 Gbps operation per link with six high-speed serial links, compliant to OBSAI RP3 (Open Base Station Architecture Initiative) and CPRI (common public radio) standards. 
  • 4 lanes of HyperLink at up to 12.5 Gbaud/lane. HyperLink is a proprietary highspeed interconnect that enables designers to implement high-speed communication and connectivity to other KeyStone devices. The HyperLink on the TCI6612 and TCI6614 works in conjunction with the Multicore Navigator to dispatch tasks to multiple devices transparently, so they execute as if they are running on local resources.
TI's KeyStone SoCs include the TeraNet hierarchal switch fabric, which the company specifies for more than
two terabits bandwidth for data transfer within the SoC. The MSMC in the TCI6612 and TCI6614 is TI's Multicore Shared Memory Controller, which allows the cores to directly access shared memory without having to use any TeraNet bandwidth. The MSMC arbitrates access to shared memory between the cores and other IP blocks, eliminating memory contention.


TI is targeting the 3rd quarter of 2011 to begin sampling the TCI6612 and TCI6614 SoCs. Solutions incorporating a digital radio front end will follow.

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