Tuesday, December 31, 2024

Idealogues vs The Semiconductor Industry

(originally posted on LinkedIn February 26, 2024)

 Introduction

Now that funding has begun, the CHIPS Act is back in the news, with the White House and the  Department of Commerce’s CHIPS Program Office (CPO) announcing $5B allocated for R&D projects and $1.5B to GlobalFoundries. Coincidentally, just a few days before these announcements, I was asked my opinions of a the proposals in a report titled Reshoring and Restoring: CHIPS Implementation for a Competitive Semiconductor Industry.  This report was published by an organization called the American Economic Liberties Project (AELP).  I hadn’t heard of the AELP before, but according to one of its recent job listings, it’s a “non-profit 501(c)3 organization dedicated to fighting monopoly power”.

In a nutshell, through its publications and other activities, AELP means to foster aggressive antitrust policies through the use of legislation, litigation, federal regulation and oversight, tariffs, and other means, with a special focus on the technology industry. While I support reasonable efforts to ensure competitive markets and counteract economic inequality, after reading the report, I hesitated to bring attention to this group and its work, owing to the numerous erroneous assumptions and factual errors I found in it.  Even worse, the authors present a defamatory characterization of leading semiconductor companies and their business practices, as well as the entire fabless-semiconductor industry. 

My first inclination was to not give such a report any further exposure. But someone who closely monitors activities in Washington brought it to my attention, and my subsequent research showed that AELP is very well connected there, having been founded by a former Treasury official now working with the FTC. According to the website Influence Watch, the group’s 2023 Anti-Monopoly Summit was attended by a number of federal officials, and the agenda included a video message from President Biden. Along with that, the report’s lead author is an academic and former mobile-industry executive now running for political office. Unsurprisingly, there’s not a single semiconductor-technology expert among the report’s authors; the other two are a lawyer and a political scientist. 

After realizing that this report might make its way into the hands of people in power, I decided to publish a more extensive critique here, where semiconductor-industry colleagues can add their expertise and comments on AELP’s proposals. This work is entirely unsponsored.

But first, I contacted the report’s lead author, inviting him to discuss what I see as its mischaracterization of the semiconductor industry, based on my 45+ years of experience in roles throughout the ecosystem. I didn’t think it would be fair to blindside him with criticisms that came out of the blue.  As you can read below, that didn’t go well.

I expect that the AELP isn’t the only such organization seeking to use the CHIPS Act to further its agenda, and while its proposals aren’t quite Sam Altman scale, the group is at least partially funded by a billionaire—Pierre Omidyar—founder of eBay. The report and its proposals serve as a great example of what can happen when idealogues, politicians, and lawyers attempt to make technology policy.  I believe readers will see that the AELP’s policy proposals are the product of its confirmation bias, rather than sound economic and technological reasoning. My rebuttal got much longer than I expected, because the more I read the 61-page document, the more falsehoods I discovered ... but you can skip all that and just scroll down to the end to judge the proposals for yourself.

The AELP Takes on TSMC

The report starts with what the author’s call the “Monopoly Of Leading-Edge Logic Chips”, based on a description of TSMC’s dominance of the foundry business. It’s well known that concern for reliance on chip fabrication in Taiwan is the primary motivation for the CHIPS Act. To explain how this happened, looking at TSMC’s history and the evolution of the fabless industry, one could identify a number of reasons why the Taiwanese company leapt into the forefront in chip fabrication.

One might point to more than thirty years of innovation, and the development of a vast collaborative chip-design ecosystem that includes advances made by EDA and IP vendors, along with the  breakthroughs in wafer-fabrication techniques created by equipment suppliers. Looking at the tremendous growth of that ecosystem, one might also conclude that pure-play foundries have been proven to be more efficient than those owned by IDMs, such as Intel and Samsung, which have fallen behind TSMC.

But the AELP authors see things differently. According to their report, these are the reasons for TSMC’s position on the leading edge of semiconductor fabrication:

“Two decades of patent abuse, exclusive deals, cheap money, and weak antitrust enforcement have gutted what used to be a crown jewel of the American economy. While there is a need for significant capital investment to sustain the semiconductor business, this consolidation is the result of business practices, not economies of scale.”

That last point really stood out… the notion that the success of the fabless-semiconductor industry, and TSMC’s leadership, have nothing to do with economies of scale. And innovation fell? I have no idea how they determined that! 

“If economies of scale were driving the needs of this industry, semiconductor firms would be building fabs to compete — as they used to do and as certain parts of the industry still do — instead of paying out shareholders.”

“If Apple, Qualcomm, or Broadcom operated in a competitive market, then margin pressures would compel them to vertically integrate…”

The AEPL apparently endorses that famous quote from Jerry Sanders, “real men have fabs”. They’re just now $20B ones.

In their attacks on the fabless model, the authors attempt to use as a comparison how memory chips are manufactured, concluding that the IDM model employed by companies like Micron Technology is more efficient, and that “Where the semiconductor industry is highly competitive, the fabless model is incompatible.” So, according to AELP, IDM = competitive, fabless = anti-competitive. DRAMs, flash memory, and logic chips all require advanced process technology, but the authors failed to comprehend how different those design and manufacturing requirements are, as well as how different the end markets are. Here’s a more appropriate comparison: in 2023, Micron reduced its CAPEX plan by 40%, to $7B, whereas TSMC’s first 3nm fab was estimated to cost $20B and its Phoenix fab will cost an estimated $40B.

Making Apple the Culprit

The AELP authors also blame Apple for making TSMC so strong, going so far as to say that without them, it would be unlikely that the foundry could “retain its key fabs in the hot zone of Taiwan”. Then, reading into the headlines about Apple acquiring all of TSMC’s 3nm production in 2023, AELP concludes that:

“The Apple-TSMC deal excludes competitors from acquiring advanced semiconductors and from building competitive fabs elsewhere”

This, after noting that Intel cancelled its 3nm orders, so they weren’t actually excluded. Nevertheless, TSMC only began booking 3nm revenue in 3Q23, when it contributed just 6% of the foundry’s quarterly income. At the same time, AMD, Qualcomm, and Nvidia (as well as Apple) were employing TSMC’s 4nm technology, and are expected to roll out 3nm chips in 2024. Also in 3Q23, Mediatek announced it had taped out its first 3nm design, for 2024 production at TSMC.  But to the report’s authors:

“It would be as if one plane manufacturer bought the entire supply of aluminum for a year.”

Not even close. Apple is just the lead customer for TSMC’s 3nm node. Rather than a case of excluding competitors, Apple accepted the risks inherent in early production, in return for small increases in performance (10-15% speed) and density (35%) compared with 4nm, and at best a few-quarter lead over competitors. Keeping in mind that a full mask set for TSMC’s 3nm process is estimated to cost $20M, it should be apparent it’s not something very many companies can afford.

But to AELP, Apple is a monopoly, by virtue of its 60% share of the U.S. smartphone market. That doesn’t meet the definition of a monopolist, and it’s an even weaker argument when taking into account that Apple’s worldwide smartphone-market share is only around 30%. Nevertheless, the report’s authors errantly assert that:

“Apple’s monopolization of smartphones means that TSMC has effectively one customer for the world’s most important chip category.”  

TSMC has just one smartphone-chip customer? The authors omit the fact that Qualcomm (holding about a 28% share of the smartphone-chip market) has historically split production of its Snapdragon processors between Samsung and TSMC, and Snapdragon processors ship in many more phones than Apple’s iPhones, as do TSMC-manufactured Mediatek chips.

AELP vs The Fabless-Semiconductor Industry

As I mentioned in the introduction, before deciding to publish this review, I first contacted the report’s lead author. By offering to discuss the report, I thought I could share my knowledge to help correct some of its errors, and address the misunderstandings of the semiconductor industry. Suffice it to say, that didn’t go well. As an example, twice I asked the author how he justified one of the report’s most defamatory allegations, which he ignored:

Fabless designers compete based on the strength of patents and exclusivity of their commercial agreements, instead of the institutional capacity of their productive facilities, their ability to deliver predictably to customers, and the excellence of their engineers.” 

Besides being a blatantly false characterization of competitive dynamics in the fabless-semiconductor industry, I take this statement as an insult to all semiconductor engineers, past and present, and the countless innovations they have created. In my brief exchange of messages with the author, I pointed out other examples of erroneous assumptions and factual errors, but got no response to those either.

Instead, I was told that I missed the point, and “There is no question that the semi industry is more concentrated and less competitive,” and that’s that. He claimed that rather than looking at the entire semiconductor industry (despite devoting more than 20 pages to it), the report is meant to address this:

“A handful of firms with market power over specific semi sub-segments stifles innovation and is a massive tax on everything downstream.”

But that’s not at all the way the report reads. There are numerous statements in it that paint the entire industry with an accusatory brush, going well beyond describing a “handful of firms”. Here’s another:

The U.S. semiconductor industry used to be competitive and vibrant, but today it is too concentrated and is plagued by many of the dangers one would expect from a consolidated sector, notably shortages, weak innovation, high prices, and the pooling of risk by a monopolist.”

Once again, weak innovation?  The industry “used to be competitive and vibrant”? In recent years, through my work as an analyst, I’ve spoken with at least fifty startup companies. That claim of weak innovation and a lack of vibrance is just nonsense. But to the AELP, the growth of the fabless-semiconductor industry is the result of lax regulation, the failure of policymakers, and financial pressures from Wall Street, which has enabled chip suppliers to create monopolies and “to avoid the expense of physical production”.  This ignores the fact that the fabless ecosystem has enabled an unprecedented wave of innovation, and the creation of hundreds of new companies that wouldn’t exist if they had to build their own fabs.

Playing a Game of Concentration

To support its claim that the U.S. semiconductor industry has become too concentrated, the AELP authors claim:

“Since 2010, intra-sector acquisitions have shrunk the number of independent U.S. semiconductor firms by over 40%. Concentration and profits rose while innovation and resilience fell.”

Here’s how the AELP authors came up with their measure of industry concentration: by removing from an odd list of 27 semiconductor companies (the “Top U.S. Chip Makers” in 2010),  the 12 that have since been acquired or merged (12/27 = 44%). That’s very clever math, but not at all a measure of industry concentration. There’s no comparison whatsoever of the number of U.S. semiconductor companies in 2010 versus 2024.  

Looking at some of the companies on AELP’s list of so-called Top U.S. Chip Makers, one is PMC-Sierra, which had multiple rounds of layoffs and had restructured just prior to its 2016 acquisition by Microsemi. Another company on the 2010 list, Atmel, was struggling as the 7th-place MCU supplier before Microchip bought it in 2016. The list also includes industry pioneer Fairchild, after recording a loss of $172M in 2016 – it was acquired by ON Semiconductor. The weak don’t survive in any market.

To actually measure industry concentration, it would be appropriate to compare the share of industry revenue of the top companies then and now, rather than the totally false and misleading picture that forms a key pillar of AELP’s argument. According to industry statistics, in 2010, the top 10 U.S. semiconductor companies accounted for 55.5% of the U.S. industry’s revenue, whereas in 2023 that number was 40.8%.

But to the authors of this report, it’s as if every logic-chip segment leader holds a monopoly:

“Fabless firms monopolize specific categories of logic chips: Qualcomm for wireless modems; Nvidia for GPUs; AMD and Intel for CPUs; and Broadcom for network and broadband chips”

Qualcomm has a monopoly in modems, so Mediatek, Samsung, Huawei... throw out your designs. AMD and Intel are co-monopolists in CPUs, more accurately a duopoly then, and they don’t compete? Forget about all the Arm-based processors in non-PC segments of the computing market, or the progress Arm is making in servers, such as Microsoft’s announcement of its Cobalt chip. Broadcom is notorious for its run-ins with the FTC, but that hasn’t exactly put Cisco and Marvell out of business. In fact, Marvell’s 2023 revenue growth rate quadrupled Broadcom’s, and now Broadcom is up against Nvidia’s surging data center networking business.

While it’s well known that Nvidia is dominant in this early stage of data center AI, it faces growing competition in that arena from a number of companies, and the AI-market overallespecially inferenceincludes many more competitors. Any claim that Nvidia’s lead is by virtue of anything other than its innovations is absurd. But since it has a monopoly in GPUs, throw away your AMD Radeon cards.

[The report also includes a ridiculous discussion of how Nvidia GPUs will cause Intel “server CPU mass extinction”, but I’ll leave that for anyone motivated to read it. It’s clear that the authors don’t understand how CPUs are still required in conjunction with GPUs, to handle AI as well as general-purpose workloads.]

Some of the alleged monopolists’ competitors do get a brief mention later in the report, in a table of logic-chip market leaders. But that’s well after the authors establish their monopoly argument, and whatever competition they acknowledge for leading-edge chips is reduced to being called weak and highly concentrated.

“Despite there being many logic chip firms, any given logic market niche is highly concentrated and often dominated by a single firm”

The cost of working in leading-edge technologies demands targeting large markets, not niches, but that’s just poor use of the terminology.  This interpretation of concentration is fundamentally flawed. As mentioned above, a 3nm mask set costs $20M, and the cost of each wafer is estimated to exceed $20,000.  Only a few companies that possess superior talents and budgets can afford the most-advanced process technologies. Of course there are relatively few companies at the leading edge, just as there are relatively few players at the leading edge of any market, whether it’s semiconductors, high-performance sports cars, fine wine, luxury goods… you name it. Despite what the AELP says, this is entirely natural. It’s called market segmentation.  There will always be more companies serving mainstream and commodity segments, and the fewest at the top of the pyramid producing premier products.

AELP’s Proposals for CHIPS Act Implementation

Having built its case for how concentrated and lacking in competition and innovation the semiconductor industry is, here are the remedies that the AELP proposes, along with my comments. Some of the proposals directly relate to technology, others to economic policy, and the rest to government oversight of private companies. 

1.       Incubate entrants with a goal of four independent, leading-edge logic foundries

This may look like a sensible idea in theory, until you look at the practical challenges of developing leading-edge semiconductor-manufacturing technologies.  The AEPL authors propose prioritizing funding for “second-tier foundries”, so they can “upgrade their capacity and sophistication over time”.

Since TSMC is already building a fab in Arizona, the AELP proposes that Apple should fund that. Whereas the authors describe TSMC as a monopoly for leading-edge technology, I assume that second-tier means every other foundry in the U.S. That leaves Intel, Samsung, and GlobalFoundries, but GF decided to stop developing leading-edge processes at the 7nm node. Upgrading “over time” would take many years. At its recent foundry event, Intel announced a goal of being “the world's No. 2 foundry”... by 2030.

Regardless of the real-world obstacles, the author’s concept of “independent” but “leading-edge” fabs is essentially a contradiction in terms, because they expect these foundries would be interchangeable. As any chip designer knows, no two processes at two independent foundries are exactly the same, even if they use the same node name (e.g. 3nm). Each has its own PDK (process design kit), a unique process recipe, with different design rules, different gate density, performance, power efficiency, yield, and so on. And at the cost of a leading-edge fab, building four of them would exceed the funds available under the CHIPS Act.

In the coming years, I don’t have any doubts that we’ll have more advanced chip fabs in the U.S. But leading edge is just that… one company will always be the leader in some respect, there can’t be four exactly the same.  Perhaps Intel and Samsung will catch up with TSMC, offering more options for manufacturing leading-edge designs. But this only gets harder and more expensive with each succeeding process node.

2.       Pass legislation to require all fabless firms to dual-source their manufacturing

“Ideally the largest fabless chip companies (Apple, Qualcomm, AMD, Nvidia, etc.) would be required to buy from multiple foundries and commit to purchase at least 30% of their global volume from U.S.-based fabs.”

The AELP favors government control such as this. But just like the proposal above, it shows their lack of knowledge and naivete regarding semiconductor technology. Setting aside the question of how the government can or should monitor a semiconductor company’s volume and manufacturing contracts, second sourcing at the leading edge means more than doubling the design cost. It would mean two different tapeouts, two different mask sets, twice the design-verification effort, double the chip qual effort.  Because some of the chips I designed went into military applications, the DoD would require a second source, but that was for chips with basically one function, like an analog-digital converter. Even then, the two chips were never identical. For leading-edge SoCs, there’s just no way. As in the first proposal, leading-edge foundries aren’t interchangeable.

3.       Include Federal Trade Commission to allocate CHIPS funding and set criteria for funding recipients

This is just adding more government bureaucracy, based on the AELP’s belief that “The semiconductor market is already concentrated and thin, with limited buyers and sellers in any given segment.” Mergers and acquisitions already go through FTC review. But AELP wants the CPO and FTC to also take into account ”any future plans for intra-sector acquisitions” of CHIPS-funding recipients.

Besides being unrealistic, this proposal is completely irrelevant to the CHIPS Act. Funding under that program only goes to manufacturers, not the fabless chip-design companies that the AELP accuses of antitrust activities.

4.       Develop thicker markets

a)      by protecting new fabs through long-term demand contracts from both government and private-sector buyers

b)      developing a set of chip-making standards that lower switching costs and promote interoperability

c)       ensuring foundries operate under a quasi-common carrier principle

On the first point, the AELP is proposing the government get involved in the terms of private-companies’ purchase contracts.  The third is just as absurd, based on the author’s mistaken belief that Apple locked out competitors from using TSMC’s latest 3nm process. It proposes that the government intervene in how a foundry allocates it supply.

But point ’b’ once again shows how politicians and lawyers are completely unqualified to make technology policy.  The notion that a government agency could define a “set of chip-making standards” for any fabrication process, not to mention a leading-edge one, is ridiculous. Any semiconductor professional knows that.

5.       Address the long-term incentives for the underlying fabless business model by:

a)      by requiring more open patent and IP licensing practices and

b)      disincentivizing extractive financial practices, like buybacks and dividends

Point ‘a’ is based on the author’s erroneous allegation that “Fabless designers compete based on the strength of patents…. (instead of) their ability to deliver predictably to customers, and the excellence of their engineers.”  The authors propose that “CHIPS funding recipients should be held to stringent requirements to openly and fairly license their patents”. But again, CHIPS funding only goes to foundries, not chip-design companies, so this proposal is irrelevant.

6.       Increase most-favored nation tariff rates on end-use chip products

With this proposal, the authors intend to address offshore assembly of finished products, mainly consumer products. The authors believe that increasing import tariffs will stimulate the creation of a more diversified OSAT (outsourced semiconductor assembly and testing) industry, causing “some portion” to move to the U.S.’s free-trade partners in the Western hemisphere. Perhaps, but only by raising costs to consumers.

7.       Legislation to create an American Semiconductor Supply Chain Resiliency Fee (ASSCR).

This proposal targets the supply chain for mature process nodes, to prevent the “possibility that Chinese or other foreign producers may dump their excess chip capacity on American markets.

“We propose that this could be done through a tax on mature-node chip products that rely almost exclusively on foreign-sourced chips”

This new fee — the American Semiconductor Supply Chain Resiliency (ASSCR) Fee — would require original equipment manufacturers to either source a certain percentage — for example, 30% — of their products’ semiconductor value added from U.S.-based fabs or pay a marginal but non-negligible fee on all products with a retail price of $300 or higher, on the order of $10-$20 dollars per device.

The authors go on to say that “Chip products could be defined as any final product where a minimum value-added of chips is used in its manufacture. The term should be defined to ensure the inclusion of the key products using mature-node chips: smartphones, cars, and other consumer electronics.

So, to implement such a tax, a government agency would need to review the BoM for every single electronic product that sells for more than $300. Looking just at modern automobiles now employing thousands of chips, and EVs increasing the amount of semiconductor content, this proposal for government review is completely unrealistic.

8.       Pass legislation to establish demand-side subsidies for electronics manufactured with domestic chips

As an alternative to the ASSCR fee, the AELP authors propose tax credits to consumers, or other incentives to OEMs for the purchase and production of products made with U.S.-manufactured chips. Finally, the authors acknowledge the logistical difficulties of ensuring domestic content, but they deem it necessary to “break the stranglehold that a handful of semiconductor firms have over the U.S. economy”. I think such a hyperbolic statement requires no further comment.

Conclusions

My analysis of the AEPL report began with a fairly typical request from a semiconductor-industry outsider, for my expert opinions of its proposals for CHIPS Implementation.  As a semiconductor-industry veteran, what were my takes on its recommendations, especially its proposed mandate for dual-sourcing, incubating new entrants, and incorporating FTC oversight?  Those proposals were relatively easy to dismiss, but then I discovered the report’s defamatory characterization of the semiconductor industry, going so far as to accuse leading chip suppliers of illegal activity. This comes from an organization that has tight connections in the federal government. I couldn’t let that go without further exposure.

The issues that the CHIPS Act are meant to address are too important for any group of ideologues to exploit. I believe that it should be obvious that this report is the result of a strong confirmation bias, but misinterpretations are one thing, deliberately misrepresenting the facts is another. The author I contacted rejected any criticism or corrections, and that is especially worrisome.

Fortunately, the good news is that organizations being put in place to administer CHIPS projects are being staffed with experienced semiconductor-industry professionals.  One such organization is Natcast, a non-profit entity created to operate the National Semiconductor Technology Center (NSTC) consortium, established by the CHIPS Act. Its executives and trustees include individuals with experience at IBM, Intel, MIT Lincoln Labs, Synopsys, and Zilog. Hopefully, more knowledgeable insights will prevail over those of biased idealogues, lawyers, and politicians.

 

 

 

Thursday, April 4, 2013

Tale of the tape outs: ARM adds the Cortex-A57 to array of FinFET test chip projects

While the foundry industry is just beginning to develop chips in a (last of Moore's scaling law) 20nm process, which adds the cost and complexity of Double-Patterning Technology (DPT) in order to achieve the smaller feature size, a race is on to catch up with Intel's more advanced 3D transistors, using FinFET technology. On Tuesday, April 2, ARM announced that they had completed a "tape out" of their highest performance next-generation processor, the Cortex-A57,  targeting a 16nm FinFET process which TSMC currently has in early development. The Cortex-A57 supports ARM's new AArch64 64-bit architecture, which designers can utilize as the "big" processor in ARM's big.LITTLE configuration, paired with the more efficient Cortex-A53, or build in multiple quad configurations for standalone high-performance applications.

ARM's latest announcement follows their December 2012 press release with Samsung, in which they described a tape out for that foundry's 14nm FinFET process, based on the high-efficiency Cortex-A7 processor. ARM collaborated with Cadence Design Systems to develop the EDA tool flow for both projects. In February, GLOBALFOUNDRIES announced a projection of simulated performance, power and area for an experimental tape out for a dual-core ARM Cortex-A9 processor, based on that foundry's 14nm-XM process design kit (PDK). GLOBALFOUNDRIES said that they expect the 14nm implementation to be capable of a 61% higher speed than the same processor in 28nm-SLP technology. Alternatively, at the same clock frequency, simulations showed that the power consumed by the 14nm design could be lowered by 62% compared to 28nm. In August 2012, ARM extended their collaboration with GLOBALFOUNDRIES for the 20nm planar and future FinFET process. GLOBALFOUNDRIES is a member of the Common Platform Alliance with Samsung and IBM, which has a goal of collaborating on development of common process technology for all three companies.

Ron Moore, Director of Strategic Accounts Marketing at ARM, says that this first implementation of the Cortex-A57 on 16nm FinFET will help the company to optimize their Processor Optimization Packs (POPs), which provide licensees with Artisan Physical IP logic libraries and memory instances. Moore says that ARM and TSMC will take the 16nm test chip to fabrication. At this early stage in foundry FinFET development, ARM and Cadence were limited to a "0.1 revision" Process Design Kit (PDK), which designates the first attempt by the ecosystem partners to assemble a usable flow, more as a learning exercise than as a production ready methodology. In the past, a "tape out" indicated that a design was signed off for production. Now, because of the complexity of advanced node process development, the first  "tape outs" are only intended as test chips.

ARM has multiple objectives for this early collaboration, says Moore, starting with getting experience with how the Place and Route tools will work for their cores in a FinFET process. With the numerous new manufacturing steps that will be employed for FinFETS, ARM must evaluate the impact on power, performance, and area, before being ready to hand off their IP to customers.

The 3-way collaboration of foundry, IP vendor, and EDA providers acts as a virtual Integrated Device Manufacturer (IDM). TSMC gets to test their process with a large functional portion of what will be a typical SoC, eventually getting feedback from the test chip silicon. The EDA vendors gain early access for learning the modifications they must make to have their tools ready along with the process.

Moore said that the team just aimed for a functional test chip at this stage, since it is too early to evaluate process corners. The 0.1 PDK will not be sufficient to discern performance. It will be at least a year before we begin to see real designs put into a FinFET process. Samsung has said that they are planning to offer risk production in their 14nm FinFET process by the end of 2013.

Related articles:

Monday, February 25, 2013

Broadcom, Maxim, Freescale and TI increase focus on small cells at Mobile World Congress

Small cells and heterogeneous networks continue to be hot topics at this year's Mobile World Congress (MWC), which kicked off today in Barcelona. We are seeing announcements from several chip vendors who are expanding their offerings in this space, with an increased focus on supporting wireless operator plans to ramp up deployment for LTE metro, enterprise and residential applications.

Broadcom has announced that they are sampling a new family of dual-mode 3G/LTE SoCs, the BCM617xx series. The BCM617xx consist of three products, the BCM61760 is designed for high capacity metro cells, the BCM61750 for enterprise small cells, and the BCM61730 for residential.

Greg Fischer, Broadcom’s VP and GM for Broadband Carrier Access, says that the BCM61760 can support 100 to 200 simultaneous LTE users, and 32 to 64 for 3G, depending on the combination of radio access technologies that an operator employs. The BCM61730 can support 8 to 16 users in a residential setting.

In LTE mode, the BCM617xx enables carrier aggregation, for a maximum total of 40MHz of channel bandwidth. The SoCs support LTE CAT-4, with 150Mbs Down Link (DL) and 50Mbps Up Link (UL) data rates, and 128 active users, or 3G data rates of 42Mbps DL and 11Mbps UL, with 32 simultaneous users. Both Frequency Division Duplexing (FDD) and Time Division Duplexing (TDD) modes are supported in the BCM61750 and BCM61760.

Broadcom has partnered with Radisys to support their 4G Trillium LTE TOTAL eNodeB software on the new 4G LTE small cell modems. The software integration provides a pre-integrated solution for implementing Radio Resource Management (RRM), Self-Organizing Network (SON), Operations/Administration and Maintenance (OAM) and 3GPP-compliant protocol stacks.

For the existing 3G WCDMA residential market, Broadcom is also introducing the BCM6163, which integrates the digital base band processor and RF transceiver into a single SoC. The BCM6163 provides HSPA data rates at up to 21.6 Mbps. Broadcom is planning volume production for the BCM61630 later in the first-half of 2013.

Eric Hayes, Broadcom VP of Marketing for Processor and Wireless Infrastructure, says that the company has also developed a multi-mode small cell platform that leverages the latest 28nm processors from their former NetLogic group, which will enable customers to build more complex systems for Multiple Radio Access Technology (multi-RAT) networks. . At MWC, Broadcom is demonstrating a combined 3G/4G/"5G" solution, the "5G" being Broadcom's marketing label for IEEE 802.11ac WiFi, which operates in the 5 GHz band. Hayes says that the XLP-208 multicore processor can manage all radios and data traffic, and provides scalablity for delivering edge-of-network revenue-generating services, such as content caching, ad insertion, as well as supporting traffic management for tuning backhaul links. Broadcom says that the development platform includes Broadcom’s complete portfolio of backhaul devices for optimized traffic management, including x-DSL, x-PON and wireless.Broadcom is sampling the platform now, and is planning to support volume production in Q2.


Thursday, February 21, 2013

Samsung details Exynos Octa at 60th ISSCC

Samsung discussed details of their Exynos Octa processor design at the
2013 IEEE International Solid State Circuits Conference

Samsung raised the bar for CPU core count in mobile application processors at the 2013 IEEE International Consumer Electronics Show in Las Vegas, with their announcement of the next-generation Exynos Octa. The Exynos Octa will incorporate ARM's big.LITTLE configuration times four, with one large quartet of high-performance Cortex-A15 cores trading off operation with a smaller quartet of power-saving Cortex A7s. This week, at the 60th International Solid State Circuits Conference (ISSCC) in San Francisco, Samsung's lead designer provided some more detail on the new SoC, in a presentation of "28nm High-K Metal Gate heterogeneous quad-core CPUs for high-performance and energy-efficient mobile application processor".

Tuesday, February 12, 2013

ARM and Synopsys collaborate for Cortex-A57 virtual prototype

In late October last year, at ARM's TechCon event in Silicon Valley, ARM announced the first processor cores to be built with their next-generation 64-bit v8 architecture, the Cortex-A57 and Cortex A-53. Now, in order to enable early development of software in parallel with hardware development, Synopsys has announced the addition of the ARM v8 processors to their Virtualizer Development Kits (VDKs). Tom De Schutter, Senior Product Marketing Manager for System Level Solutions at Synopsys, says that the two companies have extended their collaboration agreement to include ARM's Fast Models for the v8 architecture.

Customers can use the VDK to boot-up operating systems, and to develop firmware and device drivers, prior to availability of silicon or FPGA hardware prototypes.The virtual models support analysis of multicore architectures, and provide developers with tools to optimize their code for maximum energy efficiency. Semiconductor companies can develop virtual models to provide to their customers for application development, without giving away any details of the chip design.For a complete SoC, users can combine Synopsys DesignWare IP models with the ARM core VDKs.

Synopsys and ARM are initially making Cortex-A57 virtual prototypes available, and the company's roadmap is to add the Cortex-A53 and support for the ARMv8 big.LITTLE methodology later. The emphasis at this point is still primarily on mobile device applications, with support for a Linux kernel and the Android operating system on the virtual platform. Schutter says that some of Synopsys' customers are using the virtual models to develop Windows on ARM, but that is not an out-of-the-box solution. The VDK supports use of ARM's debugger, along with tools from Lauterbach and GNU.

Synopsys made no mention of development of VDKs for ARM server applications, and is initially targeting customers who will be migrating from the ARM v7 32-bit architecture. The company is doing some initial exploration of server-type applications, says Schutter, such as utilizing Ethernet-connected VDKs to develop communications and network interfaces between multiple ARM-based processors.

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