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Altair Semiconductor and AsiaTelco have announced development of a TD-LTE mobile hotspot for China Mobile, which incorporates Altair's TDD/FDD LTE chipset - the FourGee-3100/6200. This is the second TD-LTE device announced by the two companies, following their demonstration in June of a TD-LTE USB dongle. The FourGee-3100 is Altair's LTE baseband chip, which the company packages in a 9x9mm VFBGA package. The FourGee-6200 provides the companion LTE RF front-end, in a 8x8mm QFN package.

China Mobile displayed the ALM-F190 TD-LTE hotspot at ITU Telecom World in October
According to the Altair press release, the "ALM-F190 is the first Mobile Hotspot product designed for both TD-LTE and FDD-LTE, capable of delivering 100Mbps downlink and 50Mbps uplink." Specifications for the hotspot device were not provided, but Chinese news website http://www.gansudaily.com.cn published the picture above, which was taken at the recent ITU Telecom World event in Geneva.

The Altair 3100 utilizes the company's proprietary O²P Software-Defined Radio (SDR), to support both FDD and TD-LTE in any band from 700-2700MHz. Altair also claims the capability for dynamic handover between FDD and TDD, a feature which could be especially important to Sprint with their recently announced multiband LTE strategy.

Related articles:
  • Has Altair taken over the lead from Sequans to supply TD-LTE chips for China Mobile?
  • Altair Semiconductor - Last (base)Band Standing?
  • Sprint CEO Dan Hesse at the Open Solutions Conference: expects seamless hand-off for multiple LTE bands
An illustration of a 32nm transistor (left) in which the current (yellow dots) flows in a plane underneath the gate.
On the right is a 22nm 3-D Tri-Gate transistor with current flowing on 3 sides of a vertical fin. (source Intel)

Intel Executive VP David Perlmutter will conclude the Monday February 20 morning plenary session to kickoff the 2012 International Solid State Circuits Conference (ISSCC) with a presentation on "Sustainability in Silicon and Systems Development". Perlmutter will be preceded by two other speakers who will also address the conference theme of “Silicon Systems for Sustainability". 

STMicroelectronics Senior Executive VP/GM Carmelo Papa will speak on "The Role of Semiconductors in the Energy Landscape", followed by Yoichi Yano, Executive VP at Renesas Electronics, who will present "Take the Expressway to Go Greener" - focusing on the role of Flash-based MCUs in automotive applications.

Intel will then provide designers at ISSCC with a deeper technical review of two of Perlmutter's key technologies for lower energy systems, 3D tri-gate (FinFET) transistors in 22nm CMOS, and near-threshold-voltage logic. In the first of their 13 papers at ISSCC, (and 4 out of of 8) in the Monday afternoon session on Processors, Intel will dive into Ivy Bridge - which they first described at their Developer Forum in September:
  • 3.1: A 22nm IA Multi-CPU and GPU System-on-Chip
Also in the Processor session, at 3:15 PM, Intel will present:
  • 3.4: 32nm x86 OS-Compliant PC On-Chip With Dual-Core Atom® Processor and RF WiFi Transceiver
ISSCC press materials describe the SoC as a dual-core 1.6GHz Atom® processor with a "custom interconnect fabric, integrated voltage regulators, clock generator with SSC, PMU and a fully integrated RF WiFi transceiver", which the company has implemented in a 32nm high-k/metal-gate CMOS process.

Intel will present their near-threshold-voltage logic design in:
  • 3.6: A 280mV-to-1.2V Wide-Operating-Range IA-32 Processor in 32nm CMOS,
The chip is described as consuming 2mW at 0.28V with a 3MHz clock, increasing to 737mW at 1.2V when operating at 915MHz.. This will be followed by more details on the 22nm Ivy Bridge design:
  • 3.8 A Reconfigurable Distributed All-Digital Clock Generator Core With SSC and Skew Correction in 22nm High-k Tri-Gate LP CMOS
ISSCC attendees will be able to see a demonstration of Ivy Bridge and the 280mV processor at the Industry Demonstration Session (IDS), to be held on Tuesday February 21st from 4 to 7 PM.

On Tuesday morning, February 21st, in a session on Wireless Transceiver Techniques, Intel will present
  • 9.4 A 20dBm 2.4GHz Digital Outphasing Transmitter for WLAN Application in 32nm CMOS
The design is described as "an out-phasing transmitter for WLAN applications that delivers +20dBm output power at 2.4GHz, while reaching 22% power-added efficiency at -25dB error-vector magnitude with an all-digital phase modulator in 32nm CMOS."

Also on Tuesday, Intel will present 3 papers in the session on High-Performance Digital, starting with more details of their 22nm design work in:
  • 10.1: A 280mV-to-1.1V 256b Reconfigurable SIMD Vector Permutation Engine With 2-Dimensional Shuffle in 22nm CMOS
followed by:
  • 10.3: A 1.45GHz 52-to-162GFLOPS/W Variable-Precision Floating-Point Fused Multiply-Add Unit With Certainty Tracking in 32nm CMOS
  • 10.4: A 2.05GVertices/s 151mW Lighting Accelerator for 3D Graphics Vertex and Pixel Shading in 32nm CMOS
In the parallel session on Sensors & MEMs Tuesday morning, Intel will describe the use of bipolar devices within the 22nm FinFET process:
  • 11.8: Ratiometric BJT-Based Thermal Sensor in 32nm and 22nm Technologies
Intel has 2 of the 4 papers on the agenda in the Tuesday afternoon session on High-Performance Embedded SRAM, both describing further examples of 22nm Tri-Gate design:
  • 13.1: A 4.6GHz 162Mb SRAM Design in 22nm Tri-Gate CMOS Technology With Integrated Active VMIN-Enhancing Assist Circuitry
  • 13.3: Capacitive-Coupling Wordline Boosting with Self-Induced VCC Collapse for Write VMIN Reduction in 22-nm 8T SRAM
The first paper is described as a "tri-gate 6T-SRAM with the smallest bit cells (0.092μm2 for high density and 0.108μm2 for low voltage) demonstrated to date and 175mV lower Vmin and 1.7× faster performance than 32nm designs." In the 2nd paper, Intel will present a "8T-SRAM that leverages intrinsic device and interconnect coupling capacitance to boost wordline voltages without level shifters, charge pumps, or separate supplies."

Following the Embedded SRAM session, Intel will present a low-power 22nm tri-gate Digitally-Controlled (ring) Oscillator (DCO) with <1mW/GHz dissipation over a frequency range of 0.20 to 3.20GHz in the session on Digital Clocking & PLLs
  • 14.4: A TDC-Less ADPLL With 200-to-3200MHz Range and 3mW Power Dissipation for Mobile SoC Clocking in 22nm CMOS
Intel's final paper at ISSCC comes in Wednesday morning's session on RF Frequency Generation, in which they will describe a 32nm RF divider with fractional frequency division ratio, all-digital calibration to suppress spurs.
  • 20.6 A 32nm CMOS All-Digital Reconfigurable Fractional Frequency Divider for LO Generation in Multistandard SoC Radios With On-the-Fly Interference Management
Related articles:
  • Samsung to Top List of Industry Presenters at 2012 International Solid State Circuits Conference
  • Micron & Intel collaborate for future-generation DRAM technology with 3D ICs 
  • Intel claims 4-year lead in 22nm Tri-gate, takes shots at GlobalFoundries and TSMC
 
The 2012 International Solid State Circuits Conference, annually the industry's premier venue for presentations on new developments in the integrated-circuit industry, will return to the San Francisco Marriott Hotel February 19-23, 2012 with the theme of "Silicon Systems for Sustainability". Samsung will lead the group of 69 industry papers at ISSCC, with contributions to 15 papers, followed by Intel with 13. A total of 202 papers will be presented by companies, universities and research institutes, spread nearly evenly with 34% of presentations from the Americas, 36% from the Far East, and 30% from Europe.

Samsung will lead off the conference on Monday afternoon, chairing the session on High-Bandwidth DRAM & PRAM. PRAM or Phase-change Random-Access-Memory, is a new form of non-volatile memory which Samsung has developed as a successor to NOR Flash technology. In PRAM, the change in logic state is based on the resistance difference of two phases (crystalline and amorphous) in a diode-like structure.

ISSCC organizers chose not to publish abstracts this year, but the advance program shows that Samsung will present two papers on 30nm DRAM design in the session:
  • 2.1: A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme
  • 2.4:  A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM With Input Skew Calibration and Enhanced Control Scheme
Analog designers may find themselves switching between the RF Techniques and Audio and Power Converters sessions on Monday afternoon, where at 2:30 PM Samsung will present:
  • 5.3: A 0.028% THD+N, 91% Power-Efficiency, 3-Level PWM Class-D Amplifier With a True Differential Front-End
Immediately following, in the session on RF Techniques at 3:15 PM, Samsung and the Korea Advanced Institute of Science and Technology (KAIST) will present:
  • 4.5: A Fully Integrated Dual-Mode CMOS Power Amplifier for WCDMA Applications
KAIST will once again have a very strong presence at ISSCC, with authorship on 14 papers, tying the Imec research institute, headquartered in Leuven - Belgium, for most papers from research institutes.

Samsung will complete their sweep of the Monday ISSCC sessions with 3 papers on the agenda for Medical, Displays and  Imagers:
  • 6.1: (with KAIST) A Sampling-Based 128×128 Direct Photon-Counting X-Ray Image Sensor With 3 Energy Bins and Spatial Resolution of 60μm/pixel
  • 6.4: A Capacitive Touch Controller Robust to Display Noise for Ultrathin Touch Screen Displays
  • 6.5: (with imec) A 160μA Biopotential Acquisition ASIC With Fully Integrated IA and Motion-Artifact Suppression
 On Tuesday morning, in the session on Multi GB/s Receiver and Parallel I/O Techniques, Samsung has a paper scheduled at 10:15 AM, which they co-authored with the Pohang University of Science and Technology:
  • 7.4: An 8GB/s Quad-Skew-Cancelling Parallel Transceiver in 90nm CMOS for High-Speed DRAM Interface
On Tuesday afternoon, February 21st at 1:30 PM, in the session on Multimedia & Communications SOCs, Samsung will share details of their next-generation application processor for mobile devices in:
  • 12.1: A 32nm High-k Metal Gate Application Processor with GHz Multi-Core CPU
ISSCC press materials describe the Samsung processor (per Samsung on 11/25/2011):
"In Paper 12.1, Samsung presents a 32nm Exynos™ application processor with multi-core CPU and GPU engines employing multiple power planes, a 1MB L2 cache, and thermal sensors to efficiently manage power across the die."
Samsung will also participate in the Tuesday afternoon session on Digital Clocking & PLLs at 3:15 PM, with:
  • 14.1: A 0.004mm2 250μW ΔΣ TDC With Time-Difference Accumulator and a 0.012mm2 2.5mW Bang-Bang Digital PLL Using PRNG for Low-Power SoC Applications
On Wednesday morning, February 22 at ISSCC, Samsung and KAIST will again present a co-authored paper in 20+GB/S Wireline Transceivers & Injection-Locked Clocking:
  • 19.7: An All-Digital Clock Generator Using a Fractionally Injection-Locked Oscillator in 65nm CMOS
In parallel, Samsung will have 3 papers in the session on Image Sensors on Wednesday morning:
  • 22.6: A 14b Extended Counting ADC Implemented in a 24MPixel APS-C CMOS Image Sensor
  • 22.7: A 1.5Mpixel RGBZ CMOS Image Sensor for Simultaneous Color and Range Image Capture
  • 22.9: A 1920×1080 3.65μm-Pixel 2D/3D Image Sensor With Split and Binning Pixel Structure in 0.11μm Standard CMOS
Finally, Samsung will present its 15th paper at ISSCC in the Wednesday afternoon session on Non-Volatile Memory Solutions:
  • 25.5 A 64Gb 533Mb/s DDR Interface MLC NAND Flash in Sub-20nm Technology
Samsung will also participate in the live Industry Demonstration Session at ISSCC 2012, on Tuesday February 21st, from 4 to 7 PM. Attendees will be able to view demos of Samsung's new application processor (12.1), the acquisition ASIC from the Medical, Displays and Imagers session (6.5), and the 1920×1080 2D/3D Image Sensor (22.9).

Related article:
Imec finds that FinFETs outperform planar CMOS for SRAM yield
Visitors to Verizon's Application Innovation Center in San Francisco
are treated to this spectacular view of the Bay Bridge.

Verizon Wireless recently invited a few members of the mobile technology media/analyst corps to their 12,000 square foot Application Innovation Center (AIC) in San Francisco, which they opened for business in August 2011. The AIC is located in the heart of San Francisco's rapidly growing application developer community, and offers three private labs along with an RF isolation room that is connected directly to the Verizon LTE Innovation Center in Waltham, MA.  By working with Verizon at the AIC, developers can gain early access to devices, and early access to wireless network APIs and software tools from other Verizon  partners. 

Since Verizon Wireless is jointly owned by Verizon Communications and Vodafone, the AIC provides an opportunity for the San Francisco facility to connect with the newly opened Vodafone Silicon Valley "Xone" R&D Center, approximately 25 miles south in Redwood City. The two companies are planning to work on joint projects that would give developers access to the combined worldwide customer base.

Verizon is experimenting with a network API that would enable web developers to
access and adjust core network performance to optimize application performance.

The connection between Verizon's East and West Innovation Centers gives application developers access to an isolated, experimental LTE Network. The RF isolation room ensures no interference with the local commercial wireless networks, while providing a backhaul connection from San Francisco to Massachusetts that essentially duplicates the setup in Waltham.

Using the Innovation Center network, Verizon is experimenting with a new network API that would allow web developers to utilize Application-Driven Quality (ADQ) of Service (QoS). The ADQ gives application developers access to core network performance parameters such as jitter, latency, bandwidth, and application priority. In a demonstration of adjusting bandwidth for a streaming music video, selecting the red "Turbo" button quickly opened up more bandwidth to eliminate pixelization. Verizon is working with Ericsson for the eNodeB base station, and Tekelec for the policy manager.


NVIDIA demonstrated the vSMP features of the Tegra-3 with a Glowball game demo at AIC

With the proximity to Silicon Valley, it makes sense that Verizon is also working with chip companies such as NVIDIA and Qualcomm, to give application developers access to new processors before they are available in commercial devices. As an example, although NVIDIA had separately shared information with the press subject to a November-8 embargo date, company representatives freely demonstrated the variable Symmetric Multiprocessing (vSMP) capabilities of the quad core Tegra-3 (aka 'Kal-El') processor during the November 1st AIC event.

Naratte's Zoosh is an ultrasonic technology which enables NFC-like functions for any device with a microphone and speaker.
In other demonstrations at AIC, Silicon Valley-based Naratte showed how their Zoosh technology can serve as a replacement for other Near Field Communication (NFC) techniques, which currently require new radio chips to be added to smartphones and other devices. Zoosh adds only software, utilizing an ultrasonic technique to transmit bursts of data at frequencies just above the range of human hearing.  According to co-founder and Chief Development Officer Byron Alsberg, Zoosh works with any device, even feature phones, which contains a microphone (to receive) and a speaker (to transmit). Naratte engineers have characterized a wide range of devices, with different transducer characteristics, to ensure that their ultrasonic technique works even in an acoustically noisy environment.

In a demonstration with a typical Verifone Point-of-Sale POS terminal, Naratte was able to add a cheap USB microphone to enable use of Zoosh. The Zoosh software can be used outside of an application, such as with a coupon that a consumer can download and redeem at the POS. Application developers can also integrate Zoosh for in-app payment. Since Zoosh uses the existing hardware that is incorporated in every cell phone, it is essentially agnostic to device, offering the potential to easily add mobile payment and other features that are typically associated with NFC.

Verizon Wireless co-owner Vodafone is developing a home gateway device to enable users to access
personal and premium content on multiple screens in and out of the home.

Verizon's connection with Vodafone opens up access for developers to that company's customers in Europe, the Middle East, Africa, and Asia Pacific. At AIC, Vodafone showed a project they are working on with Disternet, an "off the radar" company based in Richmond, British Columbia, which is developing a multi-screen TV everywhere type solution for broadband network operators. Though little is known about Disternet at this point,  the company was created in 2008 by executives who were previously founders of L3 Technology and Mobidia.

Sam Armani, Director of Product Management at Disternet, showed two example setups that utilized the company's hardware and the Vodafone/Verizon development network to enable sharing of media both in and out of the home on a variety of devices. The Disternet-Vodafone box is an internet gateway device which essentially allows operators to extend the edge of their networks into the home, without the expense of adding capability to their core network. Armani emphasized that the Disternet solution is Over The Top (OTT), making use of a consumer's existing broadband internet service. Disternet is like a micro Content Delivery Network (CDN), she said. Vodafone and Disternet are currently conducting a field trial of their system in Spain, with a commercial launch planned for 2012.

With the Disternet gateway, subscribers can access personal media, or on demand content, in and out of the home on any device, potentially anywhere in the world, says Armani. The Disternet gateway can connect to Network Attached Storage (NAS), and performs real-time transcoding for devices that are registered and have their parameters stored in the box.  Subscribers can then share content with family and friends through a secure web browser interface. In the demo, video and music content were shared across tablets, laptops, smartphones and the home TV.  One user can be watching personal media, while another can simultaneously rent a movie from the service provider.  Regarding the sensitive issue of Digital Rights Management on copyrighted content, a Vodafone spokesman said that the company has "things in place to manage DRM that they can't talk about yet".

Armani said that Vodafone is looking at Disternet as a service enablement platform. In the Spanish trial,  Vodafone has utilized the Disternet gateway to enable users to connect to the online Vodafone music store service. The demonstration also showed integration of Skype, by connecting a USB camera connected to the Disternet box, for live picture-in-picture video conferencing while simultaneously viewing other video material.
Fabless WiFi chip supplier Quantenna, based in Fremont, CA, has announced what they claim is the first availability of a chipset and reference design for the forthcoming 802.11ac addition to the IEEE WiFi Standard. IEEE 802.11ac, which promises transmission speeds of at least 1 Gbps, is one of several projects of the IEEE 802.11 Working Group. The group has scheduled final ratification in December of 2013.

Quantenna says that by using a 4x4 Multiple-Input Multiple-Output (MIMO) design, they have been able to develop a 2 Gbps wireless router reference design. The company's press release states that Quantenna optimized their solution for a variety of retail consumer electronics products including wireless routers, access points, and high-end consumer electronics devices.The QAC2300 is a two-chip solution that couples the new  4x4 MIMO digital baseband chip for 802.11ac with Quantenna’s QT2518B radio frequency (RF) chip, which already supports 802.11ac.

Quantenna's QAC2300-RDK reference design supports the future IEEE 802.11ac Gigabit WiFi standard
Quantenna has developed  the QAC2300-RDK reference design to support the current draft of the IEEE 802.11ac standard, but will make any adjustments necessary to conform to final specification. The company is making the kit available to its early access customers, along with the schematics, layout, and a set of design guidelines. The reference design is dual-mode, dual-band, enabling concurrent operation of 5 GHz 802.11ac along with 2.4 GHz 802.11n, with PCI-e or dual Reduced Gigabit Media Independent (RGMII) interfaces.

Semiconductor intellectual property provider ARM Holdings has recently been promoting a "big.LITTLE" strategy, which enables System on a Chip (SoC) design to be based on multiple heterogeneous core processors that share the same architecture, but are scaled to fit the needs of various performance level tasks. For highest performance, ARM has introduced their Cortex-A15 MPCore™ processor, which designers can mix with the Cortex-A7 for maximum energy efficiency. ARM is now similarly increasing the options for integration of graphics processor cores, with the addition of the Mali-T658 to their next-generation Midgard family of GPUs.

The ARM Midgard family of GPU cores target higher
performance beyond the Mali-400MP, which Samsung
has used in their Galaxy SII smartphone.
The Mali-T658 is the 2nd configuration that ARM has launched in their Midgard architecture, which the company targets at high-end applications, following on the Mali-T604 introduced at TechCon last year. Devices based on Midgard are still in development, while Samsung has introduced the Galaxy SII smartphone which incorporates a quad-core Mali-400 GPU based on the lower performance 1st generation Mali Utgard architecture. Jem Davies, Fellow and VP of technology in the Media Processing Division at ARM, says that Mali-400 has also done very well in the Smart  High-Definition TV market.

Besides addressing the increasing demand for high-definition graphics in mobile devices, Davies  foresees the Mali Midgard GPUs serving as the compute engines for a range of applications that can benefit from a high degree of parallel processing, extending the notion of the right core for the right task. He says that the ability to use the Mail-T658 in an 8-core configuration will make it suitable for use in High-Performance Computing (HPC) applications such as cryptography, speech recognition, and computational photography.

Although not the main focus of ARM's strategy, Davies says that fundamentally there is no reason that Exascale computing could not also be a target for the Midgard GPUs, a market where ARM-licensee NVIDIA has been making a major effort. In HPC, power consumption is still a critical issue, but at the scale of MegaWatts of electrical usage. It is interesting that ARM has timed their GPU announcement for the same week that NVIDIA has finally officially announced Tegra-3, after that  company published several key pieces of their 5-core variable symmetric multiprocessing (vSMP) architecture in recent months. The Tegra-3 integrates four 1.3GHz Cortex-A9 cores that can be operated in various configurations to maximize power efficiency,  with a 5th core of the same ARM v7 architecture to handle lower performance tasks at up to a 500MHz clock rate - a prime example of ARM's big.LITTLE vision. Tegra-3 also integrates a 12-core NVIDIA GeForce GPU.

Ian Smythe, Director of Marketing for Mali, says that the Mali-T658 is currently in the hands of several of ARM's partners who are just beginning to develop SoCs. Whereas ARM designed the Mali-T604 to be scalable from 1 to 4 cores, the T658 can be used in configurations of 1 to 8 cores, split into two parallel groups of 4 cores that each share a L2 cache.  Smythe and Davies says that users can expect to see 4X the T604 performance from doubling the number of GPU cores in the T658, along with the doubling of the number of arithmetic pipelines that ARM has incorporated into the new design. They say that the Mali-T658 will provide a 10x performance increase over the Mali-400.

ARM's vision for the Mali-T658 multi-core GPU extends to an octal configuration, in 22nm processes, in 2015.
Davies could not reveal any data concerning a power consumption comparison between T604 and T658, except to say that doubling power in order to double performance would not be accepted by their customers, so that ARM must get more efficient. Although ARM's customers will fabricate the Mali cores in a variety of semiconductor processes, Davies expects that the full 8-core configuration will not be utilized until 22nm processes come online. ARM expects a 5-year lifetime for the Midgard architecture, and their future vision for SoCs with octal GPU configurations goes out to a 2014-2015 timeframe. Davies expects customers to first take advantage of the increased arithmetic capability in the Mali T-658, before employing a parallel expansion with more cores, depending on how much silicon area they wish to dedicate to graphics.

ARM emphasizes that the Mali T-658 cores have been co-designed, co-verified and optimized from a system point of view, so that they will play seamlessly with the Cortex-A15, Cortex-A7 and the use of CoreLink Cache Coherency. The 64-bit architecture is ready for the recently announced ARMv8 64bit CPU architecture.

Related article
  • The Mali GPU, and ARM's 5-year strategy to dominate visual computing

    Apache Design Solutions, now a subsidiary of Ansys, has announced the addition of new technology  to the company's PowerArtist-XP software for developing a RTL Power Model (RPM). The company is targeting low-power applications such as mobile devices, where power budgeting is especially critical. 

    RPM provides designers with a set of tools to predict power behavior directly from the register-transfer-level (RTL) description of a design, enabling decisions to be made earlier regarding power delivery networks (PDN) and IC packaging, prior to actual physical implementation. A user begins with PowerArtist-XP, which takes as input the RTL description, RTL test vectors, .lib and parasitic models.The RPM option then takes the output from PowerArtist's analysis and applies a proprietary algorithm, which Apache calls Fast Frame Selection, to identify a few power-critical cycles from millions of simulation vectors - one frame for di/dt and another for peak current. Vic Kulkarni, senior vice president of RTL business at Apache Design, says that Fast Frame Selection provides a 10-30X run time advantage over conventional time-based RTL power analysis. Each frame may contain 20 to 100 cycles, depending on a user's requirements, says Kulkarni.


    RPM performs pre-synthesis power analysis by RTL inferencing, modeling common power format (CPF) or unified power format UPF, and computes average and per cycle power. Parasitic estimation in RPM is performed by the PowerArtist Calibrator and Estimator (PACE), which uses Apache's proprietary data mining and characterization techniques on a reference design that has completed physical implementation. Kulkarni says that users typically run PACE once on a given technology node, and the resulting power estimated from RTL with PACE is within 15% of gate-level analysis with Standard Parasitic Exchange Format (SPEF).

    Designers can use the output from RPM as input for Apache's RedHawk dynamic voltage drop analysis tool. With Current Waveform Construction, RedHawk converts cycle-average power data per supply from RPM into a transient current waveform per power source. Designers can then use RedHawk with RPM to perform early stage static and dynamic analysis of power delivery networks (PDN), and to create a chip power model (CPM) for further AC and DC package power integrity analysis in Apache's Sentinel tool.

    Availability
    Apache will sell RPM as an option to PowerArtist-XP. The company is targeting a production release in Q1 of 2012, and is currently in several early customer engagements.

    Related article:
    • Apache Design's Andrew Yang, on the ANSYS acquisition and simulation-driven product realization.
    Sprint Nextel has been widely criticized after their October 7th 4G strategy conference, where the company outlined an expensive and complex shift to LTE, and away from their current 4G WiMAX provider - Clearwire. The company added more confusion to the strategy by announcing they had signed a "memorandum of understanding" (MOU) with Clearwire to cooperate on development ot TDE-LTE.  It was against this backdrop that Sprint CEO  Dan Hesse responded to warm applause as he began his keynote presentation at the company's Open Solutions Conference (OSC) in Santa Clara on November 3rd, saying "I can tell I'm not at a shareholder's meeting"!

    Hesse started by talking about the company's view of their brand, stating "what we really stand for is simplicity and value". He emphasized Sprint's goals of simplifying the customer experience, and also simplifying the core business through the "Network Vision" strategy to build one base station platform that integrates multiple networks and frequency bands. Success of the latter strategy will be critical to deploying an LTE architecture that may include as many as four different air interfaces; Sprint's 1.9 GHz for FD-LTE, LightSquared's hybrid satellite-terrestrial 1.6GHz FD-LTE, redeployment of 800MHz, and Clearwire's 2.5-2.6 GHz TD-LTE.

    Hesse acknowledged that concerns for the $10B expense of Network Vision are partially to blame for depressing the company's stock price, along with subsidy expenses for bringing on Apple's iPhone that will lower projected earnings through 2013. While many investors are only looking at the short-term, he said, "we want to be the best wireless company" and "you can't run your company based on what Wall Street is looking for this quarter". 

    Sprint has accelerated the development of Network Vision, which Hesse said will benefit both 3G and 4G services. The company expects to cover 250M POPs with LTE by the end of 2013, with half of that number by the end of 2012. This is equivalent to a two-year reset from the company's previous Clearwire strategy, in which Hesse had earlier declared 2010 as "the year of 4G", with 120M POPs that were to be covered by WiMAX by the end of that year. Now, Sprint WiMAX devices will be sold only though the end of 2012, with a commitment for support  through the end of customer contracts.

    At Sprint's OSC, Hesse described how the LTE ecosystem is poised to become larger than WiMAX, providing a benefit from the scale of a common 4G standard throughout Europe and North America. With the MOU to develop TDD-LTE with Clearwire, Hesse said that Sprint will be able to leverage the best of both worlds, since TDD-LTE in China and India may eventually be an even larger market than FDD-LTE. He said that the two companies first had to work out the network hand-off architecture, and now need to develop a commercial agreement and a handset technology roadmap. Regarding spectrum hosting, such as the 1.6GHz LightSquared LTE band, Hesse expressed the hope that other owners of unused spectrum would see the advantage of utilizing Sprint's Network Vision, rather than deploying their own "greenfield" network.

    In response to a question from the EE Daily News on how Sprint will go to market with multiple LTE bands, Hesse said we can expect to see both multi-band devices, and devices dedicated to a particular air interface and service. In 2012 Sprint will have dual-mode CDMA/LTE handsets. Going beyond the initial 1.9GHz LTE offering, Hesse said that it is possible that Sprint will offer devices with chipsets that support both 1.6GHz from LightSquared and 1.9GHz. Breaking down the frequency bands into low/medium/high, Hesse said this offers Sprint maximum flexibility. The low 700-800MHz band is good for building penetration, while the high 2.5GHz Clearwire band is great for "tonnage". The PCS 1.9GHz spectrum is very efficient for high volumes but Sprint's plan over time, Hesse said, is for a seamless hand-off from low to medium to high for maximum coverage and the best user experience.

    Related articles:
    • Clearwire's Silicon Valley WiMAX Innovation Network
    • Sprint shuns Clearwire with muddled 4G LTE network vision
    • LightSquared CEO: We want to be the DUMBEST wireless broadband pipe.

    Sanjiv Ahuja, CEO of LightSquared

    In a keynote address on the opening day of the Open Mobile Summit in San Francisco, Sanjiv Ahuja - CEO of LightSquared, made his case for how his company plans to disrupt the wireless industry with a satellite-terrestrial network and wholesale business model.

    Ahuja started by recalling the very beginning of the mobile industry, describing Martin Cooper's first cellphone call in 1973 as a publicity stunt that was intended to convince the FCC to allocate spectrum to private industry. The irony of this assertion apparently went unnoticed by Ahuja, but was probably ill-considered coming at a time when LightSquared is also waiting for FCC approval for their plan to use spectrum in the L-Band, adjacent to GPS frequencies.

    The LightSquared CEO went on to compare the current state of mobile broadband to the beginning of the internet, saying that it took Amazon, Facebook and Google to show people that the web was useful, and then eBay and Twitter to "topple decades old dictatorships".

    Ahuja then referred to well-known statistics about the growth of mobile data traffic, saying that with smartphones consuming 25X more data and growing at a 50X rate, there are "too many devices and too little capacity", and we are "on track to run out of capacity over the next 2 to 3 years".



    The solution, according to Ahuja, is that a  different business model is required, and that - he said - is what LightSquared is trying to do with its 59MHz of spectrum dedicated to terrestrial  and satellite services. 
    We want to bring a pure utility, to commoditize it and drive down prices.
    Ahuja claimed that his plan to provide network access on a wholesale basis was an advantage, because he would not be competing with his customers who bear the expense of vertical integration. While LightSquared's hybrid satellite and terrestrial network architecture may be different, this wholesale model for providing wireless network capacity is exactly the same as Clearwire, also a 4G provider to Sprint. Clearwire, however, has an advantage with an average of 150MHz of completely terrestrial-based spectrum.

    Session moderator Mohan Gyani began the post-presentation Q&A by asking how LightSquared could be successful as a dumb pipe, when other wireless operators are struggling to avoid being relegated to the status of  basic utilities. In response, Ahuja empasized that he wanted to be very clear about this strategy, saying
    “We want to be the DUMBEST wireless broadband pipe. I want NO intelligence in our network. None. Zero. I want the intelligence provided by our partners, people who create apps, services, and devices."

    This, said Ahuja, is an opportunity to disrupt the model that has existed ,"to upset the incumbents". Since LightSquared partner Sprint would be considered one of those incumbents, and LightSquared has no plan to offer their service directly to consumers, this confrontational posturing versus the incumbents is questionable.


    During a demonstration at the Verizon Application Innovation Center in San Francisco,
    the wireless operator showed how new network APIs can be used by application developers
    to access resources to optimize transmission of video.

    While LightSquared may have no desire to build intelligence into their network, delivery to consumers requires that someone will. The LightSquared keynote address came just a day after Verizon Wireless put on a press tour of their new Application Innovation Center In San Francisco. In one of the demonstrations, Verizon showed how a new network API would enable an application developer to access network resources that could be used to optimize video transmission. By not building such intelligence into their network LightSquared may be able to keep their operating costs lower, but that just means that responsibility for assuring Quality of Service (QoS) will fall to their customers, with the cost passed on down the line to consumers.

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