Monday, November 21, 2011

Samsung to Top List of Industry Presenters at 2012 International Solid State Circuits Conference

The 2012 International Solid State Circuits Conference, annually the industry's premier venue for presentations on new developments in the integrated-circuit industry, will return to the San Francisco Marriott Hotel February 19-23, 2012 with the theme of "Silicon Systems for Sustainability". Samsung will lead the group of 69 industry papers at ISSCC, with contributions to 15 papers, followed by Intel with 13. A total of 202 papers will be presented by companies, universities and research institutes, spread nearly evenly with 34% of presentations from the Americas, 36% from the Far East, and 30% from Europe.

Samsung will lead off the conference on Monday afternoon, chairing the session on High-Bandwidth DRAM & PRAM. PRAM or Phase-change Random-Access-Memory, is a new form of non-volatile memory which Samsung has developed as a successor to NOR Flash technology. In PRAM, the change in logic state is based on the resistance difference of two phases (crystalline and amorphous) in a diode-like structure.

ISSCC organizers chose not to publish abstracts this year, but the advance program shows that Samsung will present two papers on 30nm DRAM design in the session:
  • 2.1: A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme
  • 2.4:  A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM With Input Skew Calibration and Enhanced Control Scheme
Analog designers may find themselves switching between the RF Techniques and Audio and Power Converters sessions on Monday afternoon, where at 2:30 PM Samsung will present:
  • 5.3: A 0.028% THD+N, 91% Power-Efficiency, 3-Level PWM Class-D Amplifier With a True Differential Front-End
Immediately following, in the session on RF Techniques at 3:15 PM, Samsung and the Korea Advanced Institute of Science and Technology (KAIST) will present:
  • 4.5: A Fully Integrated Dual-Mode CMOS Power Amplifier for WCDMA Applications
KAIST will once again have a very strong presence at ISSCC, with authorship on 14 papers, tying the Imec research institute, headquartered in Leuven - Belgium, for most papers from research institutes.

Samsung will complete their sweep of the Monday ISSCC sessions with 3 papers on the agenda for Medical, Displays and  Imagers:
  • 6.1: (with KAIST) A Sampling-Based 128×128 Direct Photon-Counting X-Ray Image Sensor With 3 Energy Bins and Spatial Resolution of 60μm/pixel
  • 6.4: A Capacitive Touch Controller Robust to Display Noise for Ultrathin Touch Screen Displays
  • 6.5: (with imec) A 160μA Biopotential Acquisition ASIC With Fully Integrated IA and Motion-Artifact Suppression
 On Tuesday morning, in the session on Multi GB/s Receiver and Parallel I/O Techniques, Samsung has a paper scheduled at 10:15 AM, which they co-authored with the Pohang University of Science and Technology:
  • 7.4: An 8GB/s Quad-Skew-Cancelling Parallel Transceiver in 90nm CMOS for High-Speed DRAM Interface
On Tuesday afternoon, February 21st at 1:30 PM, in the session on Multimedia & Communications SOCs, Samsung will share details of their next-generation application processor for mobile devices in:
  • 12.1: A 32nm High-k Metal Gate Application Processor with GHz Multi-Core CPU
ISSCC press materials describe the Samsung processor (per Samsung on 11/25/2011):
"In Paper 12.1, Samsung presents a 32nm Exynos™ application processor with multi-core CPU and GPU engines employing multiple power planes, a 1MB L2 cache, and thermal sensors to efficiently manage power across the die."
Samsung will also participate in the Tuesday afternoon session on Digital Clocking & PLLs at 3:15 PM, with:
  • 14.1: A 0.004mm2 250μW ΔΣ TDC With Time-Difference Accumulator and a 0.012mm2 2.5mW Bang-Bang Digital PLL Using PRNG for Low-Power SoC Applications
On Wednesday morning, February 22 at ISSCC, Samsung and KAIST will again present a co-authored paper in 20+GB/S Wireline Transceivers & Injection-Locked Clocking:
  • 19.7: An All-Digital Clock Generator Using a Fractionally Injection-Locked Oscillator in 65nm CMOS
In parallel, Samsung will have 3 papers in the session on Image Sensors on Wednesday morning:
  • 22.6: A 14b Extended Counting ADC Implemented in a 24MPixel APS-C CMOS Image Sensor
  • 22.7: A 1.5Mpixel RGBZ CMOS Image Sensor for Simultaneous Color and Range Image Capture
  • 22.9: A 1920×1080 3.65μm-Pixel 2D/3D Image Sensor With Split and Binning Pixel Structure in 0.11μm Standard CMOS
Finally, Samsung will present its 15th paper at ISSCC in the Wednesday afternoon session on Non-Volatile Memory Solutions:
  • 25.5 A 64Gb 533Mb/s DDR Interface MLC NAND Flash in Sub-20nm Technology
Samsung will also participate in the live Industry Demonstration Session at ISSCC 2012, on Tuesday February 21st, from 4 to 7 PM. Attendees will be able to view demos of Samsung's new application processor (12.1), the acquisition ASIC from the Medical, Displays and Imagers session (6.5), and the 1920×1080 2D/3D Image Sensor (22.9).

Related article:
Imec finds that FinFETs outperform planar CMOS for SRAM yield

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