Monday, November 21, 2011

Intel at ISSCC 2012: David Perlmutter keynote, details on 22nm tri-gate design and Ivy Bridge demo

An illustration of a 32nm transistor (left) in which the current (yellow dots) flows in a plane underneath the gate.
On the right is a 22nm 3-D Tri-Gate transistor with current flowing on 3 sides of a vertical fin. (source Intel)

Intel Executive VP David Perlmutter will conclude the Monday February 20 morning plenary session to kickoff the 2012 International Solid State Circuits Conference (ISSCC) with a presentation on "Sustainability in Silicon and Systems Development". Perlmutter will be preceded by two other speakers who will also address the conference theme of “Silicon Systems for Sustainability". 

STMicroelectronics Senior Executive VP/GM Carmelo Papa will speak on "The Role of Semiconductors in the Energy Landscape", followed by Yoichi Yano, Executive VP at Renesas Electronics, who will present "Take the Expressway to Go Greener" - focusing on the role of Flash-based MCUs in automotive applications.

Intel will then provide designers at ISSCC with a deeper technical review of two of Perlmutter's key technologies for lower energy systems, 3D tri-gate (FinFET) transistors in 22nm CMOS, and near-threshold-voltage logic. In the first of their 13 papers at ISSCC, (and 4 out of of 8) in the Monday afternoon session on Processors, Intel will dive into Ivy Bridge - which they first described at their Developer Forum in September:
  • 3.1: A 22nm IA Multi-CPU and GPU System-on-Chip
Also in the Processor session, at 3:15 PM, Intel will present:
  • 3.4: 32nm x86 OS-Compliant PC On-Chip With Dual-Core Atom® Processor and RF WiFi Transceiver
ISSCC press materials describe the SoC as a dual-core 1.6GHz Atom® processor with a "custom interconnect fabric, integrated voltage regulators, clock generator with SSC, PMU and a fully integrated RF WiFi transceiver", which the company has implemented in a 32nm high-k/metal-gate CMOS process.

Intel will present their near-threshold-voltage logic design in:
  • 3.6: A 280mV-to-1.2V Wide-Operating-Range IA-32 Processor in 32nm CMOS,
The chip is described as consuming 2mW at 0.28V with a 3MHz clock, increasing to 737mW at 1.2V when operating at 915MHz.. This will be followed by more details on the 22nm Ivy Bridge design:
  • 3.8 A Reconfigurable Distributed All-Digital Clock Generator Core With SSC and Skew Correction in 22nm High-k Tri-Gate LP CMOS
ISSCC attendees will be able to see a demonstration of Ivy Bridge and the 280mV processor at the Industry Demonstration Session (IDS), to be held on Tuesday February 21st from 4 to 7 PM.

On Tuesday morning, February 21st, in a session on Wireless Transceiver Techniques, Intel will present
  • 9.4 A 20dBm 2.4GHz Digital Outphasing Transmitter for WLAN Application in 32nm CMOS
The design is described as "an out-phasing transmitter for WLAN applications that delivers +20dBm output power at 2.4GHz, while reaching 22% power-added efficiency at -25dB error-vector magnitude with an all-digital phase modulator in 32nm CMOS."

Also on Tuesday, Intel will present 3 papers in the session on High-Performance Digital, starting with more details of their 22nm design work in:
  • 10.1: A 280mV-to-1.1V 256b Reconfigurable SIMD Vector Permutation Engine With 2-Dimensional Shuffle in 22nm CMOS
followed by:
  • 10.3: A 1.45GHz 52-to-162GFLOPS/W Variable-Precision Floating-Point Fused Multiply-Add Unit With Certainty Tracking in 32nm CMOS
  • 10.4: A 2.05GVertices/s 151mW Lighting Accelerator for 3D Graphics Vertex and Pixel Shading in 32nm CMOS
In the parallel session on Sensors & MEMs Tuesday morning, Intel will describe the use of bipolar devices within the 22nm FinFET process:
  • 11.8: Ratiometric BJT-Based Thermal Sensor in 32nm and 22nm Technologies
Intel has 2 of the 4 papers on the agenda in the Tuesday afternoon session on High-Performance Embedded SRAM, both describing further examples of 22nm Tri-Gate design:
  • 13.1: A 4.6GHz 162Mb SRAM Design in 22nm Tri-Gate CMOS Technology With Integrated Active VMIN-Enhancing Assist Circuitry
  • 13.3: Capacitive-Coupling Wordline Boosting with Self-Induced VCC Collapse for Write VMIN Reduction in 22-nm 8T SRAM
The first paper is described as a "tri-gate 6T-SRAM with the smallest bit cells (0.092μm2 for high density and 0.108μm2 for low voltage) demonstrated to date and 175mV lower Vmin and 1.7× faster performance than 32nm designs." In the 2nd paper, Intel will present a "8T-SRAM that leverages intrinsic device and interconnect coupling capacitance to boost wordline voltages without level shifters, charge pumps, or separate supplies."

Following the Embedded SRAM session, Intel will present a low-power 22nm tri-gate Digitally-Controlled (ring) Oscillator (DCO) with <1mW/GHz dissipation over a frequency range of 0.20 to 3.20GHz in the session on Digital Clocking & PLLs
  • 14.4: A TDC-Less ADPLL With 200-to-3200MHz Range and 3mW Power Dissipation for Mobile SoC Clocking in 22nm CMOS
Intel's final paper at ISSCC comes in Wednesday morning's session on RF Frequency Generation, in which they will describe a 32nm RF divider with fractional frequency division ratio, all-digital calibration to suppress spurs.
  • 20.6 A 32nm CMOS All-Digital Reconfigurable Fractional Frequency Divider for LO Generation in Multistandard SoC Radios With On-the-Fly Interference Management
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