|Achronix is targeting the Speedster22i FPGA at high-performance communication markets, such as 100G Ethernet|
Suppliers of Field-Programmable Gate Arrays (FPGAs) frequently attempt to differentiate their products from Application-Specific Standard Products (ASSPs), by citing the performance advantages and flexibility of programmable logic. The parallel processing and hardware acceleration features of FPGA fabrics, and their high-performance Input-Output (I/O) interfaces, are often used as a complement to software-programmable ASSPs, particularly in Digital Signal Processing (DSP) applications. However, that flexibility comes at a cost, as FPGAs are much less silicon-area efficient than purpose-built fixed-function designs.
For FPGA vendors, the answer has been to add hardened cores to their devices, essentially producing hybrids that mix programmable and fixed functions on the same chip. Standard I/O interfaces, such as the Peripheral Component Interconnect Express (PCIe), have been prime candidates for such "hardening". The new generation of FPGA Systems on a Chip (SoCs) go one step further, bringing embedded ARM Cortex-A9 cores onto the chip alongside programmable logic.
In an announcement on April 24, FPGA supplier Achronix Semiconductor described their intent to take this FPGA hybrid approach into the high performance communications market, with their line of Speedster22i FPGAs. Achronix CEO Robert Blake says that the '22' represents the 22nm manufacturing process node, and the 'i' stands for Intel - who is supplying their Tri-Gate FinFET process, and has also partnered in the engineering of Speedster. Blake says that Intel provided design assistance for core Intellectual Property (IP) building blocks in Speedster, such as the I/O, embedded memory and Phase-Locked Loops (PLLs), and is also supplying the high pin-count packaging, test and qualification services.
In the architecture of Speedster, Achronix and Intel have produced a design that is highly targeted to applications such as 100 Gigabit Ethernet (100GbE), by hardening the Media Access Controller (MAC) and Serializer-Deserializer (SERDES), as well as the PCIe, Interlaken, and DDR-3 memory interfaces. Interlaken is an interconnect protocol, originally designed by Cisco and Cortina Systems, that is optimized for high bandwidth packet transfers.
Blake says that by dedicating functions narrowly for their target communications and test markets, Speedster22i is positioned more closely to the $11B ASIC/ASSP market, at half the cost and power of other high-density 28nm FPGA solutions. This means that the competition is not just Altera and Xilinx however, as this narrow focus also places Achronix more directly up against network ASSP vendors, such as Broadcom. In a coincidence of announcements, Broadcom detailed their own new highly-integrated device for 100GbE - the BCM88030 network processor, also on April 24 at the GlobalPress Electronics Summit in Santa Cruz, CA.
The first version of the Speedster22i family that will be available is the HD1000. Achronix is planning to begin shipping engineering samples in Q3 2012, and is offering an early access program to help customers migrate from traditional FPGAs to Speedster 22i. The early access program will include PCIe evaluation boards, onsite training and technical support. According to Blake, Achronix will also offer reference starting point designs for the evaluation board, in the Q3 time frame.
The HD1000 will vie with the Xilinx multi-chip 2.5D Virtex-7 2000T for the title of the industry's highest capacity FPGA, with over 1 million effective Look-Up Tables (LUTs) and 84Mb of embedded RAM. Only 700,000 of the HD1000 LUTs are programmable, however, as Achronix attributes the rest to the equivalent functionality in the hard core embedded IP blocks.
Achronix is also developing a Speedster22i HP family for higher performance, with the Achronix picoPIPE self-timed architecture, and operation up to 1.5 GHz. The Speedster22i HP FPGAs will comprise two models, the HP360 and HP560, targeted for feed forward data flow and DSP applications. Achronix is planning availability for the HP family in Q1 2013. The larger HP560 will provide 250 thousand LUTs, and 64 Mb of embedded RAM, along with the same hard IP cores of the HD1000.
|In an example application, the Achronix HD1000 could be used to implement a 200Gbps Ethernet line card|
Broadcom 100GbE Network Processor - Eliminating the FPGA
Achronix's Blake described an example application for the Speedster HD1000, in a 200Gbps Ethernet line card. The HD1000 could provide dual 100GbE MACs, to connect to off-chip C form-factor pluggable (CFP) optical transceivers. On-chip Interlaken interfaces can provide the connection to the backplane switch fabric interface.The FPGA's programmable logic could then be used to provide packet classification, and queuing functions, to offload a network processor.
In contrast, Broadcom's development of the BCM88030 is designed to eliminate the need for external FPGAs, off-chip 10/40/100GbE MACs, and the external physical interface (PHY) on ethernet line cards. Dan Harding, Senior Director of Product Marketing at Broadcom, says that the BCM88030 provides the industry's first full-duplex 100GbE network processor for Carrier Ethernet applications.
The BCM88030 is a family of 40nm network processors, integrating 64 hardware multi-threaded cores operating at a 1GHz clock frequency, which Broadcom has optimized for network processing. Harding says that the design enables processing of 32 packets per core, or 2K packets at a time on a single chip, delivering 300M packets/sec performance. Broadcom integrated 40G and 100G MACs directly into the chip with 24 10G SERDES. The BCM88030 replace several chips in current designs, including an external FPGA used for Operations, Administration and Management (OAM) functions, and an IEEE-1588 Precision Timing Protocol Processor. Broadcom integrates their own engines for classification, lookups, policing, and statistics, to offload the processor cores.
Broadcom also supplies a Software Developer Kit (SDK) and source code with the BCM88030, along with a simulation model and debugger.The software supports Layer-2 or Layer-3 packet forwarding operations, Multi-protocol Label Switching (MPLS) and Transport Profile (MPLS-TP) functions, OAM, Timing and Metering.
The BCM88030 family includes a Broadcom proprietary algorithmic look up engine, which allows the use of low cost DDR-3 DRAM for Layer 2, IPv4 and IPv6 tables. Harding says that complex Access Control List (ACL) lookups, which may require matching on fields with wild cards, are often required for implementation of network security rules. Users can expand on the BCM88030 built-in algorithmic capability, with the NL566xx Knowledge-Based Processors (KBP), which came with Broadcom's acquisition of NetLogic Microsystems earlier this year.
In Broadcom's Ethernet line card example, four BCM88038 devices connect directly to external optical transceiver modules, and a switch fabric interface, to provide a total maximum of 400Gbps throughput, twice the data capacity of the Achronix example. Besides the 100Gbps BCM88038, the Broadcom product family will include a 50Gbps BCM88034, and the 24Gbps BCM88032. Broadcom says that each of the devices are now sampling, and they are targeting production volume for the second half of 2012.