Tuesday, May 1, 2012

More EDA vendor attention turns to 3D ICs, as Apache updates RedHawk

Redhawk-3DX enables concurrent analysis of multiple ICs
within a 2.5D package with silicon interposer

The release of Redhawk-3DX, by Ansys subsidiary Apache Design Inc., demonstrates the increasing attention that EDA vendors are giving to tools for stacked-die packaging in the last several months. Just one year ago, the largest EDA companies were expressing mostly "wait and see" attitudes, offering little beyond selective enhancements to their existing 2D design tools. Fast forward to 2012, and the annual Synopsys User Group Meeting (SNUG), where CEO Aart de Geus's described his company's 3D-IC Initiative, including a multitude of tools from simulation to layout, to reliability analysis and Design For Test (DFT). Similarly, at the Mentor Graphics User to User (U2U) meeting, CEO Walden Rhines included 3D IC testing and Mentor's suite of physical verification tools among his factors that will drive the "next growth wave" for EDA.

Apache is joining this wave, by making power integrity for 3D-IC flows one of the focal points of their 4th generation RedHawk release, along with extending their solution hierarchically from gate-level up to Register-Transfer Level (RTL) for in-die power analysis. Dr. Andrew Yang, president of Apache Design, Inc., and vice president and general manager of ANSYS, says that Redhawk-3DX has been completely redesigned to support 3D IC design. For example, Redhawk-3DX can now take as input the descriptions of multiple IC layouts, in different formats, and the embedded parasitic extractor will derive the power network parasitics along with models for the silicon interposer and Through-Silicon Vias (TSVs).

The simulation engine in Redhawk-3DX is now capable of concurrent analysis of multiple ICs. Dr. Yang says that the concurrent simulation feature analyzes every node in the power delivery network at each simulation time-point, across multiple die, using Apache's Chip Power Model methodology. The Chip Power Model is in SPICE format, representing only a reduced form of the power network with parasitics, without exposing any of the sensitive intellectual property regarding the circuit design details. 

Thermal analysis for reliability is also critical in stacked die packaging. According to Dr. Yang, Redhawk-3DX can perform a simplified estimation of the static thermal map throughout a 2.5D IC, taking as inputs the computed on-die power density and the boundary condition of the silicon interposer. This is not a detailed three-dimensional analysis, which would need to take as inputs the die material stack and thermal conductivity, from the vertical conduction paths beginning in the chip's metal layers down through the chip substrate and TSVs, such as is done in Gradient's tools. Like other thermal analysis tools based on snapshots of power density, the Redhawk tool will also not take into account the self-heating feedback effect, which actually lowers current density in power networks, by increasing parasitic resistance under dynamic conditions. Nevertheless, designers can get a picture of inter-die thermal interactions, by including the chip-to-chip paths through the interposer, rather than treating each die in isolation.

RTL-level Power Analysis

Apache is adding new capabilities to complement their PowerArtist product for RTL-level power analysis, which the company introduced in November last year.  Redhawk-3DX can take RTL vectors, in Value Change Dump (VCD) format, and propagate events down to logic for gate-level analysis. To further increase the accuracy of power analysis when RTL vectors are not available, Apache is adding a probabilistic state propagation function. Users can simply specify the frequency of activity at block inputs, which Redhawk-3DX will also then use to propagate state down to gate level. Designers can perform a full-chip analysis by combining any of the available models, RTL and gate-level vectors, plus vector-less estimation.

Behavioral Modeling for LDOs

Apache is adding the capability to include the behavior of low-dropout (LDO) voltage regulators, analog circuits which are commonly used to supply power to large blocks of digital logic, in their full-chip power integrity flow. By using a built-in SPICE simulator, Apache will create a behavioral time domain macro-model for LDOs, which can then be combined with other models within Redhwawk-3DX.

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