Tuesday, April 24, 2012

Xilinx develops next-generation tool suite for FPGA design - Vivado

Xilinx's Vivado IDE will provide a new cockpit for designing FPGAs, from ESL to simulation, debug, and place & route
(note: typographical errors corrected and updates from Xilinx added on 4/25/12)
Xilinx, Inc. has announced a successor to their ISE FPGA design tools, the Vivado Design Suite, which the company is targeting at silicon intellectual property (SIP) and system-centric design flows. Xilnx is positioning the new tool set as a solution for what they say will be the next-generation of "All Programmable Devices", spanning the traditional programmable logic and I/O features of FPGAs, as well as integration of Analog/Mixed-Signal (AMS) blocks, stacked interconnect for 3D ICs, and embedded ARM processing systems in FPGA SoCs.

The Vivado Design Suite provides an Integrated Design Environment (IDE) with a new set of system-to-IC level tools, built with a shared data model and a common debug environment. Xilinx is supporting standards in Vivado which the semiconductor industry has previously developed for SoC implementation, including ARM's Advanced Microntroller Bus Architecture (AMBA) Advanced eXtensible Interface 4 (AXI4) interconnect specification, Accellera's IP-XACT IP packaging metadata standard, IEEE P1735 methods for IP security and rights management, Tool Command Language (Tcl) scripting, and the Synopsys Design Constraints (SDC) format.

Physical Implementation in Vivado, inherited from HierDesign

For Vivado, Xilinx built upon the hierarchical floor planning capabilities of the "PlanAhead" tool, which came with their 2004 acquisition of Hier Design, to construct an environment for running every step in a FPGA design flow. Xilinx adopted the PlanAhead database format as the unified data model for Vivado, from Register-Transfer Level (RTL) logic, to finished, placed and routed designs. According to Ramine Roane, Director of Product Marketing at Xilinx, this enables a consistent reporting capability as users sequence through the flow, utilizing progressively more refined timing, power, and interconnect models. The unified data model also enables cross-probing across levels of abstraction to design source files.

Roane says that Vivado has the capacity to handle designs as large as 100M+ equivalent gates (more than 10M look-up tables or LUTs). The Vivado IP integrator provides a drag and drop Graphical User Interface (GUI), which designers can use to automatically interconnect IP from multiple sources in the IP-XACT format. Changes to the properties of interconnected modules, such as bus width, are automatically propagated to connected blocks by the Vivado IP Integrator tool.

Vivado supports Xilinx's 2.5D IC with Stacked Silicon Interconnect (SSI, i.e. a silicon interposer), the Virtex-7 2000T. According to Roane, all SSI customers are already using Vivado, which will take into account the routing delay through the interposer when performing place and route across die slices.

Adopting ASIC Place & Route Optimization Algorithms

Based on lessons learned from the Application-Specific Integrated Circuit (ASIC) world, Xilinx has updated the placement and routing optimization algorithms in Vivado from the simulated annealing techniques that have commonly been used in FPGAs. Vivado employs analytical optimization techniques for deterministic place and route, which utilize more complex multi-variate optimization algorithms to take into account global design parameters, such as total wire length. According to Roane, simulated annealing ran out of gas at 40nm, since such algorithms are limited to local random movements in optimizing a placement.

Vivado also incorporates Xilinx's clock-gating methodology, which allows entire slices of an FPGA, consisting of eight flip-flops and four 6-input LUTs, to be shutoff during idle periods. Designers will be able to choose specific clock groups or modules where they wish to use clock-gating power optimization. The Vivado power analysis tool will then report estimates of power consumption in the modules or clock groups. Vivado power analysis can be performed post-synthesis, or post- place and route. Vivado uses its internal simulator to estimate the toggle rate of flip-flops, to calculate estimated power.

Regarding the details of Vivado's power estimation algorithm, Xilinx provided this update:
Vivado supports Switching Activity Interchange Format (SAIF) and Value Change Dump (VCD) format to pre-populate toggle rates, or it can estimate them in a “vector-less” mode, using the logic within the netlist. Unified Power Format (UPF) is not supported at this point. The power algorithm infers clock enables for groups of sequential elements, with the goal of minimizing dynamic power with no more than a 1% utilization increase.
Vivado Place and Route supports an "out-of-context" design flow, which allows designers to implement complete sub-modules independently in a hierarchical methodology, and connect with the top level of the design after the block is finished.

Users can employ the Vivado graphical editor to modify physical placement and routing, or utilize TCL scripts. Xilinx has enabled a TCL interface to Vivado for traversing and analyzing a design, as well as for performing modifications. Roane says that Xilinx anticipates developing a community of users, who will share TCL scripts and best-practices, for possible inclusion in future versions of the tools.

Vivado ESL Design and Simulation

Vivado integrates the AutoESL C-to-RTL (VHDL or Verilog) synthesis tool, which Xilinx acquired in 2011, and will now be called Vivado HLS. Users can perform direct simulation of C-language, C++ models, or System-C in Vivado HLS. Xilinx has enhanced the performance of their Verilog and VHDL mixed-language simulator - ISim,  by 3X says Roane. New features will support simulation with C-models, and co-simulation with hardware for FPGA in the loop acceleration. By choosing blocks that have little interaction with the rest of the design, users can experience simulations speedup of up to 100X with FPGA in the loop, according to Roane. Xilinx is planning to release the hardware acceleration feature later this year.

Roane says that  AMS blocks would be good candidates for hardware co-simulation, and he also anticipates the feature to be widely used with the Zynq processor platforms. Designers could run their software on the actual Zynq ARM Cortex-A9 cores, and link to Verilog or VHDL simulation of the FPGA fabric.

Hardware/Software Co-Design in Vivado?

While designers will benefit from Vivado's hardware co-simulation of the ARM processing system and FPGA logic in Zynq, further enhancements will be needed to guide designers toward an optimal partitioning of hardware and software. Vivado HLS can convert C to RTL, but designers are left to discover on their own which portions of software would most benefit from hardware acceleration. Vivado HLS synthesis and  C-simulator does support rapid exploration of the possible benefits of parallelizing C functions in the first release.

Roane says that Xilinx is working on profiling tools, to help guide software engineers to find which functions could benefit from implementation in the FPGA fabric. He makes a point to emphasize that Vivado is not intended for use by software developers. It is targeted at speeding up the design process for RTL designers, who have implemented portions of their design in higher-level languages.

Price and Availability

Xilinx says that they engaged with more than 100 beta customers in the development of Vivado, and have partnered with more than 20 IP and EDA companies to prepare for the Vivado launch. The Vivado Design Suite version 2012.1 is currently available as part of an early access program. Xilinx is targeting a general release with version 2012.2 early this summer, followed by WebPACK and Zynq-7000 EPP support later in the year. 

The company says that ISE Design Suite Edition customers with current support will be provided the new Vivado Design Suite Editions in addition to IDS at no additional cost. Xilinx will continue to support ISE for customers targeting 7 series devices and prior generations.

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