Monday, April 16, 2012

ARM announces Cortex big.LITTLE physical IP optimized for TSMC 28nm processes

ARM Processor Optimization Packs provide augment a library of physical IP with benchmark reports and
documentation of ARM's implementation knowledge, to accelerate design with the Cortex A-series cores.

Semiconductor intellectual property provider ARM has announced availability of Processor Optimization Packs (POPs) for TSMC 40nm and 28nm processes, in nine new configurations for the Cortex-A5, Cortex-A7, Cortex-A9 and Cortex-A15 processor cores.

POPs provide ARM licensees with Artisan Physical IP logic libraries and memory instances, which ARM has tuned for use with a given A-series processor core and fabrication technology. John Heinlein, Vice President of Marketing in the Physical IP Division at ARM, says that POPs are typically targeted to high-performance applications. Hence, the POPs are based on ARM's larger, higher performance 12 track libraries, though occasionally lower power-optimized 9-track libraries are used. The optimizations which ARM performs are focused on the processor and cache controller, looking at the logic, high speed memory path, and all the performance-critical aspects.

Heinlein says that ARM's Physical IP development engineers closely collaborate with ARM processor engineers, in an iterative process, to identify the optimal results for each POP. When the optimizations are complete, the engineers produce benchmarking reports that document the exact conditions and results that they achieved for the core implementation.The benchmark reports become the second set of deliverables with the POP.  

Also included with each POP is an implementation guide, which details the methodology that ARM used to achieve their results, so that ARM's end customers can achieve the same implementation quickly and at low risk.  The implementation guide is derived from a full physical implementation, and includes information on the critical paths, the layout floor plan, and a set of synthesis, place and route guidelines. While ARM does not prescribe a specific implementation flow, according to Heinlein, they do work with each of the major EDA vendors to make sure that POPs work in their flows.

ARM does not actually tape out the POPs directly, but they do fabricate test chips, which provide verification points on individual IP.  The benchmark reports which ARM delivers in a POP are based on simulations of the fully populated GDS-II layout database, says Heinlein.

To date, ARM has 28 POP licensees, according to Heinlein. He says that approximately 50% of core licensees also license the POPs, with a mix of new and existing customers. Customer who are new to ARM IP licensing will often choose POPs, since they know they have a long learning curve, which they hope the POP  will accelerate. On the other hand, existing customers have already experienced the difficulty of optimizing their designs, so they find it valuable to license the POP when they see the results ARM has achieved.

ARM's new POP announcement is for the TSMC 28nm High Performance for Mobile (HPM) and 28nm High Performance (HP) processes. ARM is launching new POPs for the previous generation Cortex-A9 core, and also the first POPs for their newest Cortex-A7 and Cortex-A15 processors. The A7 and A15 cores together are the basis for ARM’s big.LITTLE solution for power efficient multicore design. ARM says that their lead licensee for the Cortex-A15 TSMC 28nm HPM POP is expected to tape out of its first chip in the next few months.

In addition, ARM is adding their new new Cortex-A7 POP for the TSMC 40nm Low Power (LP) process, to their existing 40nm POPs for the Cortex-A5 and Cortex-A9 processors. ARM says they are also working with TSMC to develop new POP variants for the latest high-speed options in the 40nm LP process.

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John said...

If they're going to prescribe the implementation building blocks and recipe in such fine detail, why not take the next step and offer a hard macro? Wouldn't that be less trouble and uncertainty for their customers? What are the pros and cons?

EE Daily News said...

Hi John,

ARM did announce a hard macro, for the quad-core Cortex A15, shortly after the POP announcement. That information was embargoed at the time this was written, but you can find the details on ARM's blog at Squaring the circle - Optimizing power efficiency in a Cortex-A15 processor

The hard macro is a good solution for customers who don't want to do any modifications. The POPs provide guidelines, benchmarks, and best practices, but still allow the customer to design to their own constraints, and optimize the physical design for their own SoC.