Tuesday, March 13, 2012

ARM partners with Freescale in upgrade of their smallest processor core: Cortex-M0+

ARM partnered with Freescale to develop the Cortex-M0+ core, which increases
performance while lowering power compared to the previous generation M0.

Thomas Ensergueix, CPU product manager at ARM, says that his company is targeting low power connected devices, or the "internet of things", with its new 32-bit Cortex-M0+ architecture, the smallest core in the ARM processor family. In its minimal configuration, when fabricated in a TSMC90LP process, Ensergueix says that the M0+ consumes only 9uA/MHz of clock speed. With a 1.2 volt supply, this is equivalent to ~11uW/Hz. ARM rated the previous generation M0 at 16uW/Hz, in the same 90LP process.

In rethinking the M0 architecture, ARM 's designers decided to reduce the instruction pipeline from three stages to only two. The reduction in number of gates lowers power, and also resulted in a 10% increase in performance through faster (2-cycle) branch execution, according to Ensergueix. Also, as a result of the 2-stage design, fewer power-consuming accesses of Flash memory are required.

Other performance modifications in the M0+ include single-cycle access to peripherals through the I/O interface, and a new micro-trace buffer for faster debug. ARM designed the new Memory Protection Unit to enable the M0+ to be used in secure, safety-related embedded applications, such as automotive and medical devices. The M0+ is 100% code-compatible with M0 software, using the same Thumb instruction set.

Geoff Lees, Vice President of Freescale's Industrial and Multi-Market MCU Business, says that his company collaborated with ARM on the design of the new 32-bit ARM Cortex-M0+ core. Freescale sees the 32-bit core as an ideal long term replacement for 8-bit and 16-bit cores.  "It doesn't make much sense to continue using 8-bit and 16-bit cores", says Lees, because today's design flows and  Silicon Intellectual Property (SIP) reuse methodologies are predominantly based on 32-bit ARM bus interconnect fabrics. Freescale will employ the M0+ in their Kinetis L series of MCUs.

Lees also says that MCU applications, such as appliances, smart lighting,and motor control, are all driving forward the development of a standard 32-bit ecosystem. He is seeing increasing requirements for networking connectivity in end devices, with the use of sub-GHz radios to connect to local sub-networks, which eventually connect to home and business WiFi gateways.Ultra low-power WiFi will eventually enable direct, energy-efficient wireless connectivity to be built into the end devices, says Lees. 

Freescale is currently in the validation phase for their first Kinetis L silicon, which they received earlier this year. The company plans to demonstrate the new devices at the Design West Conference in two weeks. Freescale's lead customers will be able to get samples starting in April, with general sampling in Q2, followed by full production quantities in Q3.

According to Lees, Freescale's plans for use of the M0+ core extend up to heterogeneous multi-core application processors, where the M0+ will be used to offload the main processor cores to manage peripherals, wireless connectivity , or analog/mixed-signal interfaces.

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