Forte Design Systems™ has announced that they are now shipping an updated version of their Cynthesizer™ SystemC-based HLS (high-level synthesis) software.According to the company, upgrades to the tool make it easier to design all aspects of ASICs, SoCs or field programmable gate arrays (FPGAs) from SystemC.
The new version of Cynthesizer includes an upgraded version of the Interface Generator for multi-clock systems that enables engineers to automatically generate interfaces for CDC (clock domain crossing) circuits. You can use the Interface Generator to create pre-validated SystemC source code for complex interfaces, such as line buffers, circular buffers, streaming interfaces and memory interfaces.
Forte has also developed a library of new application project templates, each of which includes transaction level modeling (TLM) and pin-level synthesizable interfaces. Designers can choose from a library of templates based on specific project needs.
The company also says that Cynthesizer’s runtime has been improved with the addition of a datapath component cache. By utilizing a “parts cache” during the HLS process, Cynthesizer will reuse components and incrementally synthesize only the portions of the design that are needed. Also, the new version of Cynthesizer allows you to implement arrays as register banks with multiplexing and access logic customized according to your design requirements.
Forte will offer demonstrations of the Cynthesizer in Booth #3417 at the 48th Design Automation Conference (DAC) June 6-8 at the San Diego Convention Center in San Diego, Calif.