Thursday, April 4, 2013

Tale of the tape outs: ARM adds the Cortex-A57 to array of FinFET test chip projects

While the foundry industry is just beginning to develop chips in a (last of Moore's scaling law) 20nm process, which adds the cost and complexity of Double-Patterning Technology (DPT) in order to achieve the smaller feature size, a race is on to catch up with Intel's more advanced 3D transistors, using FinFET technology. On Tuesday, April 2, ARM announced that they had completed a "tape out" of their highest performance next-generation processor, the Cortex-A57,  targeting a 16nm FinFET process which TSMC currently has in early development. The Cortex-A57 supports ARM's new AArch64 64-bit architecture, which designers can utilize as the "big" processor in ARM's big.LITTLE configuration, paired with the more efficient Cortex-A53, or build in multiple quad configurations for standalone high-performance applications.

ARM's latest announcement follows their December 2012 press release with Samsung, in which they described a tape out for that foundry's 14nm FinFET process, based on the high-efficiency Cortex-A7 processor. ARM collaborated with Cadence Design Systems to develop the EDA tool flow for both projects. In February, GLOBALFOUNDRIES announced a projection of simulated performance, power and area for an experimental tape out for a dual-core ARM Cortex-A9 processor, based on that foundry's 14nm-XM process design kit (PDK). GLOBALFOUNDRIES said that they expect the 14nm implementation to be capable of a 61% higher speed than the same processor in 28nm-SLP technology. Alternatively, at the same clock frequency, simulations showed that the power consumed by the 14nm design could be lowered by 62% compared to 28nm. In August 2012, ARM extended their collaboration with GLOBALFOUNDRIES for the 20nm planar and future FinFET process. GLOBALFOUNDRIES is a member of the Common Platform Alliance with Samsung and IBM, which has a goal of collaborating on development of common process technology for all three companies.

Ron Moore, Director of Strategic Accounts Marketing at ARM, says that this first implementation of the Cortex-A57 on 16nm FinFET will help the company to optimize their Processor Optimization Packs (POPs), which provide licensees with Artisan Physical IP logic libraries and memory instances. Moore says that ARM and TSMC will take the 16nm test chip to fabrication. At this early stage in foundry FinFET development, ARM and Cadence were limited to a "0.1 revision" Process Design Kit (PDK), which designates the first attempt by the ecosystem partners to assemble a usable flow, more as a learning exercise than as a production ready methodology. In the past, a "tape out" indicated that a design was signed off for production. Now, because of the complexity of advanced node process development, the first  "tape outs" are only intended as test chips.

ARM has multiple objectives for this early collaboration, says Moore, starting with getting experience with how the Place and Route tools will work for their cores in a FinFET process. With the numerous new manufacturing steps that will be employed for FinFETS, ARM must evaluate the impact on power, performance, and area, before being ready to hand off their IP to customers.

The 3-way collaboration of foundry, IP vendor, and EDA providers acts as a virtual Integrated Device Manufacturer (IDM). TSMC gets to test their process with a large functional portion of what will be a typical SoC, eventually getting feedback from the test chip silicon. The EDA vendors gain early access for learning the modifications they must make to have their tools ready along with the process.

Moore said that the team just aimed for a functional test chip at this stage, since it is too early to evaluate process corners. The 0.1 PDK will not be sufficient to discern performance. It will be at least a year before we begin to see real designs put into a FinFET process. Samsung has said that they are planning to offer risk production in their 14nm FinFET process by the end of 2013.

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