Intel Capital and Xilinx Technology Ventures. Oasys, which made its debut at the 2009 Design Automation Conference, produces the RealTime Designer tool for physical implementation of chip designs from Register Transfer Level (RTL) descriptions.
Though the size of the funding round has not been disclosed by Oasys, Xilinx states that the size of their investments are typically $1M to $3m. Xilinx has previously listed Oasys as one of the active investments of their Technology Ventures arm, in conjunction with their multi-year licensing agreement for Real Time, which the two companies announced in June, 2010.
Oasys has attracted attention in EDA circles by luring former Cadence CEO Joe Costello back into the industry as a board member and investor, after a failed attempt with analog synthesis startup Barcelona Design. Former Synopsys executive Sanjay Kaul also was an early investor, and acted as Executive Chairman for Oasys.