To upgrade the XpandR™ III, DSP Group has added processor and multimedia engines for HD video and 2D/3D graphic acceleration. XpandR SoCs integrate WiFi and WiFi Direct (dual-band 2.4GHz and 5GHz, IEEE 802.11a/b/g/n) with DECT (Digital Enhanced Cordless Telecommunications in 1.7GHz, 1.8GHz and 1.9GHz) connectivity. DECT is commonly used in voice applications such as cordless phones and baby monitors, while you can utilize the WiFi connectivity for video, audio and data communications. According to the company, XpandR III is optimized for applications such as visual telephony, VoIP, multimedia streaming, media-content sharing, and home control and monitoring.
DSP Group offers a two-chip solution for designers of multimedia devices. The XpandR III DMW96 SoC integrates a 1GHz ARM Cortex™-A8 application processor along with a 300MHz ARM926 co-processor. You can use the co-processor to manage the DECT protocol stack, to execute telephony functions, and to apply voice signal processing algorithms such as echo cancellation. The DP52 provides codec, AFE (analog front end) and PMU (power management unit) functions.
|The XpandR III DMW96 SoC integrates a 1GHz ARM Cortex™-A8 application processor with a 300MHz ARM9™ co-processor.|
The XpandR III SoC includes an ARM NEON SIMD (single-instruction multiple data) media accelerator for HD (high-definition) 1080p multi-format video. The device supports Google's WebM (VP8) format, and you can use the video encoder to implement full-duplex HD videoconferencing and video recording. The XpandR also integrates a 2D/3D graphics engine that supports Open GL ES 1.1/2.0 at 12.5M triangles/sec and 250M pixels/sec. You can use the dedicated security processor for secure boot/storage and DRM (digital rights management). XpandR supports WPS (WiFi Protected Setup), and WPA/WPA-II (Wi-Fi Protected Access).
The XpandR DDR Controller provides support for Mobile DDR (double data rate), LPDDR2 (low power DDR) and DDR2 support, 32-bit wide with up to 266MHz clock (3.75-nsec cycle). You can use the embedded LCD controller to support 24-bit displays with up to WXGA resolution @60Hz, while HDTV applications require an external HDMI transmitter for applications up to 720p60 or 1080p30. The camera Interface is capable of handling YUV (luminance-chrominance) data according to 601 and 656 standards, with up to 5MP (mega-pixel) sensors, over MIPI (Mobile Industry Processor Interface Allince) and parallel interfaces. The XpandR III is available in 16x16 496 BGA and 12x12 440 PoP packages.
|The DP52 is a companion codec/AFE/PMUfor the XpandR III SoC.|
Designers can utilize the DP52 codec/AFE/PMU to transmit and receive digital audio samples through an I2S (inter-IC sound) interface that you can connect to the XpandR processor. The audio signal chain includes a Class D speaker amplifier, two Σ-Δ codecs for high-quality audio, and two Σ-Δ full-duplex codecs for telephony use. You can utilize audio inputs with a built-in microphone amplifier and a line-in connection. Power management functions in the DP52 include a USB Li-ion interface and 3-cell NiMH/NiCd charger.
DSP Group offers WiFi and DECT module development boards, form-factor reference designs, embedded software packages and an Android-based (rev 2.3) software development kit (SDK) with reference applications for the XpandR II product line.