Monday, June 13, 2011

#48DAC reports: Asygn joins the ranks of European analog EDA startups.

A promotional video that ran prior to keynote sessions at the recently concluded Design Automation Conference used the tagline "DAC is the place to be". That certainly appears to be the case for European analog EDA startups, who annually venture across the Atlantic to make their U.S. debut. Unfortunately, they also tend to disappear from the DAC scene just as quickly. Companies such as Ansyn and Mephisto, who appeared in the 46th DAC report, were nowhere to be seen on this year's exhibitor list.

Time will tell whether this year's entrant, Asygn, can beat the odds and make a return appearance. Asygn CTO Nicolas Delorme, and Director of Sales Andrew Betts, described the company's offering as a way for designers to raise the level of abstraction of analog functions to a "system level". This has been the objective of other methods for many years, from SPICE macro models to behavioral languages such as Verilog-AMS. One of the differences, according to Delorme and Betts, is that the Asygn Tactyle time-domain simulator does not use the SPICE Newton-Raphson method. This has been an Achilles heel for previous approaches to analog modeling.

Asygn delivers a library of modeling primitives that have developed specifically for their simulator. You can place these primitives on your Cadence Virtuoso schematic, easing integration into the most popular analog design flow. Asysn says that you can easily switch views to a transistor or Verilog-A model for more detailed simulation. There is no tool for creating user-customized Asysgn models.

While many approaches have been tried for analog abstraction, they all have suffered from the same problem - how to calibrate the model against the actual circuit? This problem doesn't exist in digital flows, where library characterization tools are typically used to run batch SPICE or Fast-SPICE simulations to churn out timing models. The key performance characteristics for analog/mixed-signal  functions can not be derived so easily.  Asygn relies on the user to judge if the model is a sufficient representation of their transistor implementation. If you can't efficiently simulate the circuit in the first place, there's really no other way to do this.  However, competitors such as Berkeley Design Automation have been successful with Analog Fast-SPICE, which also works directly from a transistor-level circuit schematic.  Achieving a higher level of analog abstraction, without suffering from a accuracy-performance tradeoff, remains the holy grail in EDA.

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