|Sidense uses a 1T split-channel antifuse in their NVM IP (source Sidense)|
Earlier this week, Synopsys announced availability of their DesignWare® AEON® NVM (Non-Volatile Memory) silicon IP (intellectual property) for standard 180-nm CMOS process technologies. Synopsys makes AEON IP available for FTP (few-time programmable), MTP (multiple-time programmable), and EEPROM (electrically erasable programmable read-only memory) applications.
In the FTP configuration, Synopsys configures AEON for 256 bits of storage, and the company specifies the IP for up to 100 write cycles. Synopsys targets RFID and wireless SoC designs with AEON MTP, with an increase in write cycles up to 1,000 and capacity from 128 bits to 1kb, with low power operation that enables read operation down to 1.0 V. The company targets the AEON MTP EEPROM for automotive grades, in 64 bit to 1kb configurations, with up to one million write cycles and operation at up to 150 degrees C. The FTP and MTP IP are currently in qualification, while the EEPROM has been fully qualified by Synopsys.
On June 28, Kilopass Technology and SMIC (Semiconductor Manufacturing International Corporation) announced that they have extended their OTP (one-time programmable) NVM product offering for SMIC’s 55nm logic CMOS process. Kilopass has previously taped out their NVM IP in SMIC’s 65nm process.
Kilopass uses a 2T (two-transistor) antifuse design, and they target applications such as trimming of analog/mixed-signal functions, embedded boot code, and security keya for multimedia processors, MCUs, and RFID ICs. In April, Kilopass announced development of Itera, an MTP version of their IP for 40nm processes at TSMC, GLOBALFOUNDRIES, and UMC.
Sidense is unique in offering a 1T (one-transistor) split-channel, nonvolatile memory cell for OTP applications.With their single transistor design, Sidense claims the smallest NVM cell size in the industry. Sidense products are available from 180nm to 40nm from a number of foundries, including TSMC, UMC, Fujitsu Microelectronics Limited, SMIC, TowerJazz, IBM, GLOBALFOUNDRIES and ON Semiconductor.
Because their 1T technique does not rely on charge storage, Sidense says that their NVM is more secure than EEPROM, FLASH or Logic NVM which use floating gates. The compay says that although charge can not be seen optically, its presence can be detected (at least theoretically) with advanced sample preparation and microscopy techniques. The greatest vulnerability, according to Sidense, comes from the risk of erasure or reprogramming. Charge-storage NVM can be erased by exposure to high temperature, and their contents can be altered from the back side of the die with an electron beam, according to Sidense.
The Sidense antifuse programming method is based on inducing a structural change in the silicon to silicon dioxide interface, of approximately 10 - 25A (Angstroms) in height and 20-50A in diameter - equivalent to about 10 – 50 atomic layers. Sidense says that this structural change of the antifuse can only be detected using TEM (Transmission Electron Microscopy), which can potentially show the structural change if the cross-section cuts through the breakdown (programmed) spot, a highly laborious and time consuming process.
Sidense offers a SLP (low power) version of their 1T IP in 180nm processes, with capacity up to 256kb. The company also provides an ULP (ultra-low power) version, with up to 2kb storage, that Sidense specifies for standby power draw of less than 0.25µA with read operation down to 1.5V. For higher density applications, Sidense IP is available in densities of up to 512kb, in 130nm to 40nm processes.
Designers have a lot to choose from in deciding on a vendor for non-volatile memory IP. Your choice will depend on compatibility with your fabrication process, with 180nm as the current sweet spot for NVM. From there, other factors come into play, such as reprogrammable or one-time programmable, security and low power. The table below provides a comparison of offerings from the vendors discussed in this article.