Tuesday, February 12, 2013

Tensilica adds Image/Video Processor to DSP IP core offerings

Tensilica's IVP is a complete image and video processing subsystem

At the 2013 International Consumer Electronics Show (CES) in January, semiconductor companies engaged in a daily competition to one-up each other with announcements of their next-generation application processors. Advances in imaging and video capabilities were central to those announcements, as NVIDIA rolled out Tegra-4 with 72 GPUs, along with a dedicated computational photography engine for High Dynamic Range (HDR) still image and video recording. Qualcomm followed with their announcement that the Snapdragon 800 Series will support UltraHD video. In their CES press conference, Intel demonstrated advances in User Interfaces (UI), including recognition of finger gestures and eye movement.

It is ironic that Texas Instruments predicted many of these developments three years ago, in a plenary talk ("Harnessing Technology to Advance the Next-Generation Mobile User-Experience") at the International Solid States Circuits Conference (ISSCC), and they now exit the mobile device segment just as the applications are becoming a reality. Greg Delagi, the TI Senior VP who delivered that talk at ISSCC in February 2010, now says that his company will focus on the embedded market (such as "smart cars"), where embedded vision and graphics applications are also expected to grow rapidly but with less volatility and pricing pressure.

Tensilica introduces IVP

DSP silicon IP provider Tensilica is gearing up for these emerging opportunities, and will be demonstrating a new Image and Video Processor (IVP) at the Mobile World Congress (MWC) later this month. Chris Rowen, Tensilica’s founder and CTO, calls the IVP a "major new thrust" for his company, which previously focused on audio and baseband DSP cores. Rowen says that the targeted applications for IVP have common requirements for very high pixel rate and high levels of operations per pixel, along with the need for ease of programming to enable designers to change and upgrade image processing algorithms that continually evolve. The new imaging and video applications that the likes of Intel, Qualcomm and NVIDIA are planning to support require performance to improve at a faster rate than Moore's Law. For example, UltraHD video requires 4X the processing of 1080p video, while applications such as feature recognition or image tracking and identification demand 10X the horsepower of today's Image Signal Processors (ISP). According to Rowen, new architectures are required in order to meet the performance needs with fixed power budgets.

Tensilica will be offering their IVP as a complete subsystem, including the synthesizable core, memory system, and an instruction set which supports 8, 16, and 32 bit pixel processing. The IVP architecture will be scalable by number of element engines and processors. The company's lead customers have had early access to the IVP since last year, and with the MWC announcement Tensilica is opening it up for licensing to a broader customer base. Tensilica will be competing with UK-based silicon IP provider Imagination Technologies, known for their Power VR GPUs, who demonstrated their PowerVR vision ISP at CES, also targeting embedded vision and UltraHD video processing.

IVP Architecture and Software

A key component of any image processor is the memory subsystem. Moving massive amounts of data for frame-to-frame analysis can result in bottlenecks and processing latency. In their IVP, Tensilica allocates two 512 bit wide memory ports to the core processor for access to local data RAM, and adds a ╬╝DMA controller with an additional 512 bit wide port, for a total of 192 (8 bit) Bytes of data access per cycle.

The parallelism of the IVP Single-Instruction Multiple Data (SIMD) architecture allows for fetching of 16, 24, or 96 bits per cycle, followed by issuing up to 3 commands to the Xtensa control processor, or 4 pixel processing commands per cycle to a set of 32 element engines. Each element engine contains three 16b ALUs, a 16b X 16b multiply-add and a 16b variable shifter, along with dual 16b/8b load/store, and multiple register files. The end result is that each element engine is capable of up to 96 ALU operations, 32 multiples, or 64 element loads per cycle. A memory data rotator takes care of allocating the 512b data slices per cycle to the proper element engine.

Customers who license the Tensilica IVP package will get the synthesizable RTL and  EDA tool scripts, along with a reference testbench and set of test cases, design tools, and a Software Developer Kit (SDK). Tensilica provides an Instruction Set Simulator (ISS), Fast Function Simulator (TurboXIM),  System-C based system modeling tools, and the Xenergy energy estimator. The Software Developer Kit (SDK) provides the Xplorer IDE GUI, and a GNU Software Toolkit. The Xtensa C/C++ (XCC) Compiler includes the capability for auto-vectorization of developer's code. Tensilica includes a set of reference image processing applications and a library of operating system kernel functions.

Tensilica will demonstrate the IVP at MWC on a FPGA prototyping system, based on Xilinx Virtex-7 devices, which they will make available to customers in the coming months. The FPGA development kit includes an image sensor interface and FPGA Mezzanine Card (FMC) from Dream Chip Technologies. Tensilica has also lined up a set of image processing software partners for the IVP launch, including Morpho, Irida Labs, and Almalence.

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