SEMICON West, which completed its 42nd annual event at the Moscone Convention Center in San Francisco last week, is the premier trade-show of the SEMI industry association, representing the global semiconductor manufacturing supply chain. While much of this year's SEMICON show and technical discussions were focused on how to continue traditional Moore's Law scaling, increasing cost and technical barriers have driven the industry to turn more attention to the potential alternative for achieving higher functional integration through 3D multi-chip ICs.
In a series of presentations on the second day of the conference, invited speakers explored the topic of "The 2.5 & 3D Packaging Landscape for 2015 & Beyond". In the session abstract, SEMIS's Advanced Packaging Committee expressed their objective to explore questions such as "What will the supply chain and infrastructure look like?", in just three years. The answer, after representatives from semiconductor manufacturers, Electronic Design Automation (EDA), systems houses, Outsourced Assembly and Test (OSAT), and academics had their say... was very fragmented.
Altera and TSMC
John Xie,Senior Manager for Packaging Technology at Altera, started off the presentations at SEMICON with "Interposer Integration through Chip on Wafer on Substrate (CoWoS) Process". In March of this year, Altera announced "the world's first heterogeneous 3D IC test vehicle using TSMC's Chip-on-Wafer-on-Substrate (CoWoS) integration process". TSMC is planning to offer the CoWoS process as part of a complete turnkey service. In CoWoS, ICs are first bonded to thick silicon wafers (i.e. the interposer), prior to completion of processing for dicing and attachment to the final package. The TSMC interposer-based process is more properly described as 2.5D, and is effectively similar to the Stacked-Silicon Interconnect (SSI) process which Xilinx has employed, also with TSMC as a foundry. In May, Xilinx one-upped the TSMC-Altera announcement with one of their own, disclosing that they had shipped the "World's First Heterogeneous 3D FPGA", the H580T. In a SEMICON keynote address earlier in the day at SEMICON, Xilinx CTO Ivo Bolsens described how 3D ICs are a key to his company's strategy for delivering customer value through higher levels of integration.
Xie also stated that "true 3D" IC integration would require the implementation of Through-Silicon Vias (TSVs) in the active area of stacked ICs. However, compared to alternative 2.5D processes, Xie said that CoWoS offers the best yield potential. TSMC's process, according to Xie, is better for micro-bump joining of ICs to interposers, provides better compatibility with large die, and avoids the need to handle thin wafers. The turnkey nature of the process, however, presents an issue with how to integrate die fabricated at other foundries. The interposer can also impact device performance, and Xie expressed a concern for insertion loss from the TSV connections, especially regarding the Power Distribution Network (PDN). Altera inserts inductors to increase device bandwidth, and embeds Metal-insulator-Metal (MiM) capacitors to improve transceiver jitter by 10%. Among the challenges for 3D IC design, Xie said that EDA tools are still a work-in-progress. Cost also remains an issue, with the interposer being the dominant factor, comparable to the cost for an active silicon die.
Pessimism from HiSilicon/Huawei
In "The Demands and the Challenges of TSV Technology Application in IC & System", Dr. Huili Fu - Chief IC Packaging Expert at Huawei's ASIC design subsidiary HiSilicon Technologies, focused mostly on the challenges facing the 3D IC industry. While acknowledging the potential benefits of multi-chip packaging for achieving higher interface bandwidth and functional integration, somewhat surprisingly, Fu also stated that "Nobody wants to use 2.5D for Smartphones". Cost and package thickness are obstacles for adoption in such applications. At the top of Dr. Fu's list of 3D IC challenges were the immature TSV manufacturing process, the problems of handling thin wafers, issues with micro-bumps, and die-to-die assembly. Fu also cited challenges in testing of micro-bumps, and the test, cost and assembly issues related to use of the Through-Silicon Interposer (TSI).
Turning to 3D IC Infrastructure, Fu pointed out challenges in instituting standards, development of design flows and EDA tools, and supply chain evolution. As Altera also noted, TSVs present challenges for high-speed design, because the interposers create very lossy transmission lines. There is also inconsistency in the impedance of the routing structure, according to Fu.
There is much discussion of the use of 2.5D/3D IC integration for processor-memory applications. However, Fu cautioned that thermal cross-talk is a major problem for such heterogenous integration, for which there is no obvious solution. There is generally a junction temperature limit for memory of 85 degrees C, he said, and while there is a desire to place memory closer to logic for increased bandwidth, the sensitivity to temperature and requirements for refreshing is an obstacle. The problem only gets worse with true 3D stacking, especially for smartphones which lack top side heat sinks, according to Fu.
Current Approaches to 2.5 and 3D are too expensive
This was the view expressed by Georgia Institute of Technology professor Rao Tummala, who also asked (rhetorically), "Are There Lower Cost Options?" Of course, Georgia Tech has an answer for that question, in work being done at the university's Packaging Research Center (PRC) on polysilicon-based interposer panels.
Tummala expressed his opinion that 3D IC adoption will take off when current technologies don’t do what the market needs, or - if new technologies are lower cost, which he stated is never the case. Technically, the use of 3D ICs with TSVs is the next logical step in the evolution of IC packaging, said Tummala, but the critical difference is that 3D ICs change the IC fabrication process, because packaging would now be part of chip manufacturing.
Professor Tummala presented what he sees as three major applications for 3D ICs; in mobile devices, "ultra-high performance" computing, and high-performance devices. His example company for ultra-high performance was IBM, Xilinx and Altera for high-performance, and Apple and Samsung for mobile devices. Cost and thermal issues make 3D ICs unsuitable for high performance applications, in Tummala's assessment, while acknowledging that Xilinx has solved the thermal issue through side-by-side 2.5D packaging. Cost is still an issue for 2.5D, he said, along with the lack of a second source for manufacturing. While cost is the only issue for mobile, according to Tummala, ultra-high performance applications can accept these issues.
Georgia Tech has assembled a large number of corporate, government, and academic participants in their PRC consortium. At SEMICON, Professor Tummala argued that the industry "needs" the Georgia Tech panel approach, which utilizes rectangular polysilicon panels to fabricate interposers, in place of conventional 300mm CMOS wafers. In a 2010 webinar on their technology, Tummala estimated that a 600mm panel could support integration of 8X the number of packages as a 300mm CMOS wafer, and that the materials and processes could provide an additional 2X cost savings. The Georgia Tech approach supports a 3D stack of two or more ICs on both sides of interposer, with TSVs at the same density as the ICs. Tummala said that this presents minimal challenges in thermal management and testability.
Industry Ecosystem Panel points in multiple directions
SEMICON concluded the 3D IC session with an industry ecosystem panel consisting of:
- Samta Bansal, Senior Manager, Product Marketing, Silicon Realization at Cadence Design Systems
- Li Li, Distinguished Engineer at Cisco Systems, Inc.
- Rich Rice, Sr. VP of Sales and Engineering at Advanced Semiconductor Engineering Group (ASE) Inc.
- David Stepniak, Analog Development and Execution Packaging Manager at Texas Instruments
ASE's Rice offered his opinion that several different 3D IC manufacturing flows will be deployed:
- IDM/foundry captive processes
- Foundry fabrication with TSVs and Back-Side Integration (BSI) to OSAT assembly
- Foundry IC fabrication to interposer foundry to OSAT BSI
- Foundry IC and interposer with BSI to OSAT assembly
Cisco's Li expressed an optimistic view that 3D ICs with TSVs and large area silicon interposers are the future, with 3D stacked die fulfilling the increasing need for memory bandwidth. Cadence's Bansal called for
3D-IC ecosystem collaboration, citing examples of the Micron-led Hyper Memory Cube consortium, and the TSMC-Altera CoWoS collaboration. Bansal said that data exchange format standards and tool interoperability between companies are needed, in order to develop a “3D ready exchange Process Design Kit (PDK)”.
The panel also offered different opinions on what are the biggest roadblocks to 3D IC adoption. For TI, full-system yield is the biggest issue. With their position as an OSAT, ASE focused on how to handle ultra-thin die. Cisco expressed the need to educate ASIC and system architects on how to partition systems for 3D IC applications. For Cadence, testability is the #1 issue.
Summary: Multiple dimensions for 3D ICs
While much has been said and written about 3D ICs, as an alternative to the inevitable end of Moore's Law in semiconductor fabrication, the discussions at SEMICON show that achieving such a transition will be far more difficult than simply changing the direction of scaling. There have long been alternatives to single-die packaging, and the development of 2.5D ICs with silicon interposers is more evolutionary than revolutionary. Stacked 3D ICs will continue to be developed for narrowly targeted applications, such as the HMC stacked memory devices, but more widespread use will require much more development across the ecosystem. IDMs such as Texas Instruments will be able to develop more specialized solutions to address their integration needs. Unlike the development of the fabless IC industry, which rapidly converged around a foundation of common processes and design methodologies, the development of 2.5D/3D ICs is branching off into many different directions.
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