Sunday, March 4, 2012

EDAC executives share their vision for the industry (Part 1)

(image courtesy Ed Sperling - Editor in Chief, System Level Design)
The Electronic Design Automation Consortium (EDAC) annually gathers leaders of their biggest member companies, generally the CEOs of Cadence, Mentor, Synopsys and one or two others, to share their forecast and vision of the year ahead. This year EDAC decided to change things up by asking executives, before the event, for their opinions on a set of technical and business questions pertaining to the current and future state of the EDA industry. An unspecified number of EDAC members were polled on the same questions, and a comparison of the results was used as the basis for discussion at the meeting.

While this juxtaposition of views may be of value for identifying discord within the industry, unfortunately, it is also totally insular. For greater insight into the future of the EDA industry, it would be be more revealing to compare the views of EDA executives to those of their customers.

For this year's "Forecast and Industry Vision" panel discussion, EDAC assembled:
The moderator of the panel discussion was Ed Sperling, Editor in Chief of System Level Design.  

This is Part 1 of our report on the EDAC Executive Vision meeting, focusing on questions related to technology. In Part 2, we will focus on more business-related questions. 

3D ICs

For the first question, the panel (and EDAC members) were asked when 3D IC packaging, whether stacked die or "2.5D", where several silicon die are interconnected on an interposer,  would become mainstream. This emerging technology is seen by some as an alternative solution to traditional Moore's Law silicon scaling, which will inevitably run its course at some point. Respondents were left to their own judgment of what mainstream means in this regard. 

According to the poll results, two executives see 2013-14 as the period of mainstream 3D IC adoption, two chose 2014-2015, and one said not until 2016 and beyond. A small percentage of the general EDAC population (~5%) said that 3D ICs are going mainstream now,  in 2012, while the largest percentage (~60%) forecast 2015-2016.

Mentor CEO Wally Rhines expressed his opinion, that 90% of the value of 2.5D/3D ICs will be derived from stacking of memory die, or combinations of processors and memories, "long before" stacking of logic ICs with Through-Silicon Vias (TSVs) in the active die area becomes commonplace.  Intel and Micron Technologies, leaders in processors and memory ICs, have announced a collaboration for such a development last year, based on 3D Hybrid Memory Cube technology.

ARM's Segars raised the specter of a potentially contentious issue, competition for control of the 3D IC industry amongst packaging houses, memory suppliers, and IC foundries, each hoping to extract the most value from the development. Rhines echoed this concern in his comments, saying that foundries such as Samsung and TSMC want to provide turnkey 3D IC services, while Outsourced Assembly and Test (OSAT) companies feel they are the companies that should own the process.

Synopsys' de Geus, while pointing out the issues regarding who is responsible when a stacked device fails, said that one positive is that heterogeneous systems of mixed analog-digital components can be assembled more easily than in monolithic devices. He and Cheng agreed that EDA tool vendors are ready for 3D ICs, but that the economic issues must first be addressed by systems houses, who will presumably drive the industry when their need becomes sufficiently great. Cheng added that many of us already carry devices containing stacked memory, in the form of Secure Digital (SD) memory cards that are used in smartphones and cameras.

What is the most difficult challenge in IC design today?

For this question, respondents were allowed to choose from Integration, Software, Power, Cost or Time-to-Market (TTM) as the biggest challenge in IC design. Three of the five executives (or 60%) chose integration as the biggest issue, while only 10% of the EDAC population agreed.

Approximately 25% of the general EDAC population chose software as the biggest issue, compared to just one executive, while another executive chose TTM. There was a fairly even spread of responses across other categories from the general response, 20% for TTM and power, and ~15% for cost.

To further probe the executive majority view, Sperling asked whether the perceived problem of integration was that of the EDA vendors themselves (i.e. interoperability), or of the customers, who must typically assemble a diverse set of functional blocks and tools in order to complete a typical System on a Chip (SoC) design.  Appearing surprisingly defensive about the issue in his tool-centric response, de Geuss said:
"by definition it is the biggest issue for the customer, who very quickly figures out who the culprit is.. and that's us."
Internal EDA groups have shrunk over the last ten years, said de Geus, to the point that they can no longer work on tool integration, so the burden has reverted to the EDA industry. He went on to say that this also represents an opportunity and a challenge for the industry, one that it is "absolutely taking on".

The moderator then turned the discussion back to design integration issues, pointing out that difficulties with integration of Silicon Intellectual Property (SIP) remain as major issues for EDA customers. Cheng said that the physical interaction of SIP, through thermal "pollution", is an issue that designers have not had to think about in the past, and industry standards are need. 

Rhines said that the increasing complexity of building blocks, from transistors and gate to now complete sub-systems, has been good for the EDA industry because it requires more verification.

As a SIP provider, Segars said that his company is challenged to deliver new views and data to their customers on increasingly complex IP, and it would be beneficial if the industry could agree on what is important. 

Taking the opportunity to promote his company's recent announcement of System Verilog-based intellectual property for verification of communication interfaces, de Geus said that there is historically a cycle of innovation before alignment in the EDA industry. Referring to Cheng's discussion of thermal issues, de Geus agreed that physics and other multi-dimensional issues are now more important, but this represents "an incredible opportunity" for the industry.

What is the most prevalent IC concern for EDA customers?

With just five members on the executive panel, the tabulation of executive opinions on this question depicted an anomalous result. The distribution of answers was "power" at 50% (2.5 people?), followed by "performance" at 30% (1.5 people?), and TTM at 20% (1 panelist)

The EDAC respondents also chose power as the most significant issue, at greater than 40%, with a distribution between 10-20% for the other issues, which included Area/Cost and Other (verification).

The moderator asked the panel why power is such a great issue now. Rhines said that up until a few generations ago in process technology, performance increases came as a "freebie" with shrinking dimensions. Now, power management has evolved from a device level issue to the system and package level. 

Segars said that SoC complexity is a challenge, with so many different blocks on an SoC, and so many use cases to account for.  Tan said that the growth of cloud computing is driving a need for power savings in data centers, where companies are looking for a 5-10X improvement. This issue in data centers is exacerbated by increased adoption of mobile devices, said deGeus.

Cheng said that rather than define the problem in terms of "low power", the focus should be on energy efficiency all throughout the design hierarchy, up through the development of application software. Following on that notion, Sperling asked how EDA can break down traditional silos to address the problem more holistically.

Rhines responded by putting the onus back on the customers, saying that that Mentor has been selling tools for embedded system design for twenty years, but that adoption has been slow. He said that the reason systems companies have been able to achieve higher profit margins than component companies, is that they must have the expertise to integrate diverse technologies and make the whole package work. The problem tends to get left for later in the design, said Rhines, because it is difficult to get people who can look at the problem from multiple points of view.

What technology challenge will spur the next big growth wave in EDA?

Three of the panelists chose IP re-use and integration in their answers to this question. One chose hardware-software co-design, and one chose Electronic Systems Level design (ESL).  The general EDAC population was evenly split at about 35% on those two choices as most popular, with the rest split at approximately 15% each for ESL and "Other" (3D ICs, none). None of the executives chose the mixed-signal design option, nor did any of the general EDAC population. Segars said that the sum of all the issues should be the answer, because overall system complexity is the challenge. 

Synopsys' de Geus said that ESL has not grown faster, because it is really hard to get all the pieces to work together. He said that the design process will continue to be made up of domain specialists, because software engineers, as an example, would not want to deal with power issues at lower levels. 

Sperling responded that there would be a need for experts that can look across domains to bring the pieces together, and questioned whether such experts exist. 

"They do exist", replied de Geus, going on to say that they make the difference in enabling companies to get their products out on time.  Left unaddressed, unfortunately, was whether such experts exist at the EDA companies. Such a broad expert would also be required to architect more holistic EDA solutions.

Rhines said that growth spurts only occur in EDA when a methodology shift comes about, and that we are just now headed into a decade where a lot of methodology changes will be required. He blamed slow growth in EDA, beyond economic issues, on the lack of such methodology shifts in recent years.

See Part 2 - What will EDA look like in 5 years? EDAC, executives share their vision.

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