Tuesday, February 21, 2012

Tensilica unveils low power DSP engine for LTE-Advanced handsets

Tensilica's new BBE32UE DSP Engine is optimized for LTE-Advanced handset applications

Tensilica, a developer of Digital Signal Processing (DSP) Semiconductor Intellectual Property (SIP) cores, has announced a new ConnX BBE32UE DSP for applications in baseband processors for LTE-Advanced handsets. The company says that they have secured lead customers for the new design, which will enable development of a software-programmable Category 7 (300Mbps download,  150Mbps upload) PHY (Layer 1) with less than 200 mW power consumption (excluding Turbo decoding), when combined with Tensilica Baseband Dataplane processors (DPUs) in a 28nm HPL CMOS process.The core also supports 2G, 3G, LTE and HSPA+ standards. Tensilica has previously announced that NTT DOCOMO and partners NEC, Fujistu and Panasonic Mobile have designed LTE handset SOCs with the company's Xtensa LX DPUs.

While Tensilica will be demonstrating working silicon at Mobile World Congress (MWC) for their ATLAS LTE Reference Architecture, Eric Dewannain - VP and baseband Business unit manager at Tensilica, says that leading handset OEMs are already moving to LTE-Advanced  to get started on the typical three-year development cycle for new modems. With that long lead time from introduction of a new DSP core, the BBE16 DSP at the core of Atlas, which Tensilica announced two years ago, is just now ready for demonstration at this year's MWC. Graham Wilson, product marketing manager at Tensilica, says that the company will show a live LTE demonstration with a eNodeB base station and LTE handset, both employing Tensilica cores. The handset is said to be based on based on a Maxim SOC. In January of this year, Maxim acquired LTE ASIC design company Genasic.
The challenge for LTE-Advanced designers is how to increase performance by 3X from today's Category 3 LTE devices, without increasing power dissipation to unacceptable levels. According to Dewannain, a system redefinition is needed to scale down clock rates and offload the main DSP core.  He says that the combination of Tensilica's C-programmable BBE32UE DSP, with the company's specialized DSP task engines for functions such as Fast Fourier Transforms (FFTs) and digital filters, provides a more flexible solution than Register Transfer Level (RTL) approaches while consuming less power than general purpose DSPs. 

Tensilica optimized the DSP Architecture in the BBE32UE for user equipment applications, with a 10-stage DSP pipeline, and a hybrid Single Instruction, Multiple Data (SIMD)/Very Long Instruction Word (VLIW) Architecture. The core incorporates 32, 18-bit multipliers with 40-bit accumulators (MACs).The Vector DSP and 3-way VLIW decoder were both streamlined to minimize power in LTE-Advanced applications.  For a complete LTE-Advanced modem, designers can combine the BBE32UE with the BSP3 Bit Stream Processor and the SSP16 Soft Stream Processor, along with a set of specialized task engines. Tensilica's early access customers have access to ConnX BBE32UE now, and the company is planning a general product release for the third quarter of 2012.

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