It seems that there is a serious epidemic spreading around the globe. An epidemic of denial. The symptoms were first observed in the camps of Meego developers, who are apparently still exhibiting signs of denial regarding the death of their "open" operating system, despite Nokia dropping it to "project" status back in February. Now Intel has said they are also dropping Meego, and replacing it with yet another Linux Foundation project - Tizen.
Then today, HP published their latest email newsletter for webOS developers, with the subject heading
"Increase in TouchPad Sales Boosts App Downloads".
In a report on webOS developer meeting in Australia, Singapore and Hong Kong, HP proudly exclaimed:
... what many developers have continued to experience over these past few weeks. They are seeing more than a 10x increase in sales in their apps over the last month and the momentum is even stronger this month.
"HP will discontinue operations for webOS devices, specifically the TouchPad and webOS phones. The devices have not met internal milestones and financial targets."
So what could have stimulated a "10x increase" in webOS app sales? Well, just two days after killing off the TouchPad, HP launched a fire sale, lowering the price to $99. This was apparently enough to create a buying frenzy, so much so that HP responded by ensuring prospective buyers of More TouchPads on the Way, in a post on a company blog.
In order to clear inventory of unsold TouchPads, HP lowered the price to $99.
I wouldn't look for more TouchPads anytime soon, as HP is now sold out. Prior to its termination, analysts at iSuppli had reported the bill of materials cost for the TouchPad to be $318. With Meg Whitman now at the helm, your best bet is to look on eBay.
TI and ViewAt based the EPOS reference design
on TI's 45nm ARM Cortex-A8 processor
Texas Instruments has announced availability of a reference design for electronic point-of-sale (EPOS) applications, which they developed with ViewAt, a provider of POS and personal identification number (PIN) pad design solutions based in China. TI says that the EPOS modular design offers flexibility for customers who wish to develop products such as countertop payment terminals, mobile payment terminals with wireless support, handheld data terminals with barcode scanning, and full kiosks.
The EPOS solution is based on TI's 1GHz AM3715 ARM® Cortex-A8 microprocessor, and includes integration of a printer, cellular modems for GSM/GPRS/EDGE/CDMA, Bluetooth and Wi-Fi. Near-field communications (NFC) capabilities in the reference design are provided by TI’s 13.56-MHzTRF7970A RFID/NFC transceiver IC.
The EPOS reference design includes a (unidentified) third-party hardware security controller for secure boot and tamper protection. TI says that a pre-evaluation has been performed by UK-based testing lab RFI Global, for Payment Card Industry (PCI) Personal Identification Number (PIN) Transaction Security (PTS) standards, to enable software developers to obtain PCI-certification more quickly and to get products to market faster.
Operating systems supported in the EPOS reference design include Linux, Android and Windows Compact Embedded, although ViewAt specifies the EFT-POS VPOS53 with Microsoft Window CE 6.0 R3.
Other specifications from ViewAt:
Memory: nand flash 4Gb（256Mb*16), mobile DDR 2Gb（64Mb*32）
Display Resolution: 3.5 inch 240 × 320 Pixels / 262,000 Color
Interface:1 USB （OTG type，Host port，Client port)，1 USB（RS232port)
MOSIS, the low-cost integrated circuit prototyping and small-volume semiconductor manufacturing service, which turned 30 years old this year, is holding an Advanced Technology Workshop at the Davidson Conference Center on the University Park Campus of USC on October 31st.
David Mulligan, Sales Director at MOSIS, says that "the purpose of the meeting is to project some of the ways that access to advanced technology for the U.S. research and development community will be enabled in the coming years, and to gather and share input about how to implement these plans from the collected wisdom and experience of U.S. leaders in integrated circuit, photonics, and MEMS design, and from newer areas like carbon electronics"
The agenda for the meeting includes sessions on MOSIS fabrication processes, 3D ICs, and III-V semiconductors. You can register for the workshop on the MOSIS website.
MOSIS Advanced Technology Workshop Agenda
08:00 Breakfast, registration
09:00 Introduction - Mike Fritze, Director, Disruptive Technologies, Information Sciences Institute
14:00 Photonics and carbon electronics - John O'Brien, Executive Vice Dean of Engineering, and Chongwu Zhou, Professor - Viterbi School of Engineering at USC
Intel Labs has announced that they will establish a fifth Intel Science and Technology Center (ISTC), to be hosted at the University of Washington, which will focus on research in Pervasive Computing.The ISTCs are part of a $100M program to invest in U.S. university research, which was announced by Intel in January 2011. Previously announced ISTCs include the center for Visual Computing at Stanford, Secure Computing centered at UC Berkeley, an ISTC for Cloud Computing with a hub at Carnegie Mellon University, and the ISTC for Embedded Computing, also at Carnegie Mellon University.
Intel commits funding to the ISTCs for a period of five years (with a checkpoint at three years), along with assigning four Intel researchers per center that will work directly on the hub campuses. The ISTC collaborative model includes a set of spoke universities along with each center hub. The plan is for any intellectual property that is developed to be put into the public domain, and for any software that is developed to be open source. The co-principal investigators for the Pervasive Computing center are Dieter Fox, associate professor of Computer Science & Engineering at the University of Washington, and Anthony LaMarca, a senior scientist at Intel.
The Pervasive Computing team has chosen three research themes that will be the focus of their work:
Low-power sensing and communication
Understanding human state and activities
Personalization and adaption
To enable low power, unobtrusive sensing and communications, the ISTC plans to employ energy harvesting techniques, and to develop energy-efficient network protocols.
The goal of the second pervasive computing theme, understanding human activities, is to be able to "recognize a user’s fine-grained context and interactions with people, objects, and environments", said research Dieter Fox. Fox envisions the integration of a heterogeneous set of sensors with extensive use of cameras, integrated into mobile devices, and embedded in a user's home and the environment. During an analyst briefing preceding the announcement, Fox cited the Microsoft Kinect sensor and camera system as an example of a device that can be leveraged to extract more complex human context, through its ability to sense depth. In order to make pervasive computing real-time and efficient, the researchers will investigate how to partition execution of algorithms between mobile devices, embedded computers, nearby servers, and cloud computing.
For personalization, the goal is to have pervasive computing systems that will be interactive, and continuously learn user’s preferences, their environments, and routines, etc. The notion is for personalized models in the system to have the capacity to be taught new activities by example and demonstration. On this last theme, the researchers will need to balance on a fine line between pervasive computing and invasive computing. In a whitepaper that was published as part of the announcement, the authors note that ensuring security and privacy is a key issue in their work.
Exploring new technologies to support the next generation of pervasive computing will require dealing with significant quantities of private information. To ensure the trustworthiness and security of the systems involved and to safeguard privacy, security and privacy researchers will be involved in all of the center’s research efforts. They will serve as internal consultants who will proactively surface, assess, and address potential privacy concerns related to the technologies being explored. They will also strive to develop a deeper understanding of what trust and privacy means for each problem domain, and to develop new technological solutions for achieving trustworthiness and privacy when standard best practices are not sufficient.(From whitepaper on The Intel Science and Technology Center for Pervasive Computing).
The Pervasive Computing smart cooking assistant would have the ability to learn recipes by
observation with multiple depth-sensing cameras.
Intel's Anthony LaMarca said that the Pervasive Computing ISTC team is developing concept applications to drive their work in three different domains: mobile health and well-being, the smart home and family coordination, and task spaces.
In an example of a smart cooking assistant, LaMarca described a kitchen-oriented task space that would have knowledge of recipes, be able to keep track of cooking progress to provide reminders and guidance, interact with cooks via audio, gesture, projected imagery, and use multiple depth cameras to learn detailed nuances of new recipes by demonstration.
The example application of family coordination may evoke feelings of Big Brother, with its goal being to "help families coordinate their busy lives through monitoring, tracking and reflecting on their activities". LaMarca said that by following a family through their daily routines, such a pervasive computing system would advance the state of the art in machine learning to unsolved problems such as task interruption and task coordination, for a whole home or organization.
The mobile component of the pervasive computing project is focused on personal stress, with the goal to "help users identify, manage, and reduce stress and anxiety in their daily lives". The hope is to identify the causes of stress by using sensors in a mobile device to follow a user's daily routine. LaMarca said that crowd sourcing of data would also be leveraged to help users manage stress.
In response to the inevitable concerns for machines replacing human interaction, LaMarca said that capturing expert domain knowledge, such as for cooking, would enable bringing it to the masses in a more detailed way. Perhaps we all could have Julia Childs or Rachel Ray as kitchen companions to guide us in preparing gourmet meals. LaMarca also said that he believes that the real time learning, adaptation, and personalization capabilities of pervasive computing can be an enormous boost to personal health and wellness.
At the opening of the P&T/EXPO Comm in Beijing today, Broadcom announced availability of two new switch products in their StrataXGS line, targeting the aggregation portion of networks; the BCM56640 for modular platforms, and the BCM56540 for fixed carrier Ethernet platforms.
The new products extend Broadcom's offering for Carrier Ethernet solutions, which include the BCM88600 series for the network core, and the BCM56440 series for access and mobile backhaul networks.
The BCM56640 enables designers to employ a 240 Gbps fully-integrated multilayer Carrier Ethernet aggregation switch, to develop single-chip line cards with front panel connectivity that can support 48 Gigabit Ethernet (GbE), twelve 10Gigabit Ethernet (10GE), three 40Gigabit Ethernet (40GE), or a single 100Gigabit Ethernet (100GE) port(s). The BCM56640 includes an expansion interface that you can use to add an optional external memory to support up to 512K IPv6 longest-prefix route lookups.
The BCM56540 is a 180 Gbps fully-integrated multilayer Carrier Ethernet switch for fixed platforms. Broadcom’s flexible port logic, which they have dubbed F.XAUI (10 Gigabit Media Independent Interface), allows engineers to reassign 10GE interfaces on the fly for use as 1 GbE or 2.5GbE ports. Broadcom has developed a nw flexible forwarding technology, which allows providers to allocate lookup resources with the BCM56540 on a per-application basis, to improve the application range of a given system solution.
Jim McKeon, Product Marketing Director in the Network Switch Infrastructure & Networking Group at Broadcom, says that the transition of networks from voice-centric to data-centric challenges operators to find optimal solutions for upgrading and building out their new data networks. He says that operators have two alternatives, a less disruptive packet transport network (PTN) with the 'look and feel' of a voice-oriented network, or an internet protocol radio-access network (IP-RAN) for better long-term scalability. Broadcom has designed the new BCM 56640 and BCM 56540 to be ideally suited for both PTN and IP-RAN deployments, so that engineers can build unified systems that are not constrained by the silicon, according to McKeon.
Availability
Broadcom says that samples for the BCM56640 and BCM56540 are available now, and the company is targeting production volume for the first half of 2012.
The design for Apple's proposed new headquarters building will be a circular, spaceship-like
structure surrounding a courtyard with an internal diameter of one-third mile
At least lawyers seem to be doing well these days.The list of companies that are suing, or being sued by, Apple for patent infringement continues to grow. Soon, it should be long enough to circle the new headquarters structure that Apple is planning to build on the former HP campus in Cupertino, CA.
Today, Taiwanese processor manufacturer VIA Technologies joined the litigants, announcing they were suing Apple for infringement of:
The patents at issue cover microprocessor functionality featured in Apple iPhone, iPad, iPod, and Apple TV devices, namely:
US Patent No. 6253312, Method and apparatus for double operand load,
US Patent Nos. 6253311 and 6754810, Instruction set for bi-directional conversion and transfer of integer and floating point data.
According to a press release from VIA: "VIA has built up an extensive IP portfolio consisting of over 5,000 patents as a result of significant investments in world class technology research and development," commented Wenchi Chen, CEO, VIA Technologies, Inc. "We are determined to protect our interests and the interests of our stockholders when our patents are infringed upon."
Intel CTO Justin Rattner discusses the Hybrid Memory Cube at the Intel Developer Forum
It was slipped in for only about one-minute of Intel CTO Justin Rattner's hour-long presentation on the final day of the Intel Developer Forum (IDF), so many observers may have missed the announcement that Micron and Intel are collaborating on development of the Hybrid Memory Cube (HMC). HMC had been first introduced just one month earlier, by Micron Fellow and Chief Technologist J. Thomas Pawlowski, who gave a more detailed presentation at the Stanford University Hot Chips Conference (without disclosing the Intel involvement). Hybrid Memory Cube is a 3D IC innovation that goes beyond processor-DRAM die stacking, which has been shown by companies such as Samsung, to an entirely new architecture for the memory-processor interface.
Micron introduced the Hybrid Memory Cube at the Hot Chips Conference
at Stanford University in August.
Speaking at Hot Chips, Pawlowski said that in order to continue to increase bandwidth and reduce power and latency to meet the demands of multi-core processing, it is essential that direct control of memory must give way to some form of memory abstraction. The need to have an industry standards body, such as JEDEC, agree on the ~80 parameters used to specify DRAMs results in a "lowest common denominator" solution according to Pawloski.
In the HMC, communication from the processor to memory goes through a a high-speed SERDES data link to a local logic controller die at the bottom of the DRAM stack. In the prototype example shown at IDF, 4 DRAMs were connected by through-silicon vias (TSVs) to the logic die, but stacking of up to 8 DRAMs was also described. The processor was not integrated as part of the stack, avoiding issues of die size mismatch and thermal/cooling issues. The HMC is a complete DRAM module that can be attached in close proximity to the CPU in a multi-chip module (MCM) or on a 2.5D passive interposer. Micron also described "far memory" configurations where some HMCs connect to a host and others connect to other HMCs, through serial links to form networks of memory cubes.
HMC eliminates the need for a complex memory scheduler, using just a thin arbitrator that results in shallow queues, said Pawloski at Hot Chips. The HMC architecture eliminates complex standards requirements, since only the high-speed SERDES interface and form-factor need to be standardized. Timing constraints no longer need to be standardized, since these specifications can be tuned to the application with a custom logic IC, while the high-volume DRAM die are the same across numerous applications.
Pawlowski said that while the serial links slightly increase system latency, a significant overall reduction is achieved with HMC. The DRAM cycle time (tRC) is lower by design, and lower queue delays and higher bank availability further shorten system latency. The 1st generation HMC prototype utilizes four 40 GBps (billion bytes per second) links per cube, for a total throughput capability of 160 GBps per cube.
The Micron-Intel Hybrid memory cube achieved
Micron-Intel constructed the 1st generation 27mm x 27mm HMC prototype by combining 1Gb 50nm DRAM arrays with a 90nm prototype logic die, for a total capacity of 512MB in the DRAM cube. The resulting performance achieved significantly ~3X better energy-efficiency (in pj/bit) than next-generation DDR4. The bandwidth of 128GBps with a 1.2 volt VDD, equates to a record-breaking sustained transfer rate of >1 Terabit per second (Tbps or 1 trillion bits per second), according to Intel.
Intel claims a 4-year lead over competitors in the race to the 20nm process node.
In a session titled "22nm Tri-gate Transistors for Industry-Leading Low Power Capabilities" at the Intel Developer Forum (IDF) yesterday, Intel Senior Fellow Mark Bohr said that the company's FinFET process is 4 years ahead of competitors, including TSMC and the trio of GlobalFoundries, Samsung and IBM (i.e. Common Platform). In explaining Intel's technology lead during the Q&A session following his talk, Bohr went so far as to question whether any other company was yet shipping a high-k metal gate (HKMG) process in volume production - a technology which Intel began shipping in 2007.
GlobalFoundries process roadmap targets 20nm in Q4 2012
The comments from Bohr serve as a return volley to comments made by executives at the GlobalFoundries Technology Conference (GTC) in Santa Clara two weeks ago. In response to a question at the GTC press/analyst lunch, on the company's choice of HKMG for 20nm technology, GlobalFoundries Senior VP for Technology Gregg Bartlett commented that Tri-Gate is limited to processor-only applications, making it less suitable for the diverse requirements of SoCs. GlobalFoundries also claims to be first foundry to ship HKMG in volume.
Intel is developing an SoC version of their 22nm Tri-Gate process in parallel with the CPU version.
At IDF, Intel disputed the notion of limited applications for the Tri-Gate process, showing that Intel has been developing both CPU and SoC versions in parallel for all process nodes, starting at 32nm. The CPU process emphasizes performance, while the SoC process is optimized for lower power mobile applications.
Intel's 22nm Tri-Gate SoC process will offer a full set of features to support RF, analog and mixed-signal applications for mobile devices.
Intel is targeting production of their new Ivy Bridge processor, the successor to Sandy Bridge, in the 22nm Tri-Gate process in Q4 2011. Public availability is targeted for the first half of 2012. Intel is developing a large number of process options for 22nm Tri-Gate SoC, including higher voltage thick-gate transistors, RLC passive components for analog and RF applications, and embedded one-time programmable (OTP) memory.
Intel CEO Paul Otellini welcomes Google's Andy Rubin onstage at IDF
The Intel Developer Forum (IDF) kicked off this morning in San Francisco, starting with the keynote presentation by CEO Paul Otellini. Otellini talked about a "computing continuum" where the required attributes are "Engaging, Consistent,and Protected". On the last point, Otellini described a "partnership" with McAfee, though the company became a wholly-owned subsidiary in February. This mirrors Intel's approach to the Wind River acquisition, retaining the brand identity of the purchased company.
An executive of McAfee pointed out the challenge of "Day Zero" trojan viruses (i.e. those for which there is no history), which can install root kits that become deeply embedded at the kernel level of an operating system. A traditional software-only approach to virus protection often fails to catch such threats to PC security. The Intel and McAfee collaboration will be based on a combination of hardware and software, using behavioral monitoring to block trojans in a new, more effective solution which the companies have dubbed “DeepSafe”
Intel demonstrated this Medfield processor based tablet,
running the Honeycomb OS, in a "computing continuum" demo at IDF.
To demonstrate a computing continuum, Intel showed sharing of content from a Android-based smartphone and tablet, with images appearing on a "family wall". The PC is still at the center of the application connected framework, which Intel said will ship in devices such as a Toshiba Ultrabook PC by the holidays, enabling a consistent connected user experience.
It is apparent that Intel is backing away from the Meego operating system, which they announced in a collaboration with Nokia just about one and a half years ago. With Nokia now moving to Microsoft Windows 7 mobile operating system, Meego is about to become another orphan OS. Nevertheless, Intel has two Meego-related sessions scheduled for later today and tomorrow at IDF.
In a surprise, Otellini disclosed that the smartphone that was used in the demo is Medfield-based, and is a working prototype which is being made available now to development partners. Otellini said:
We have learned a lot of things about smartphone silicon and device design. We want to make the Intel architecture the platform of choice.
Finally, Otellini announced a collaboration with Google, bringing VP of Android Engineering Andy Rubin onstage to declare that all future versions of Android will be optimized (no doubt non-exclusively) for the Intel architecture. With ARM-based processors continuing to dominate the mobile space, it will be interesting to see if this belated shift to Android bears fruit in the near future.
The Altera transceiver development board for the 28nm Stratix V GX FPGA is available for $4,995.
Altera Corporation has announced availability of a signal integrity development kit for the 28nm Stratix® V GX FPGA SERDES (serializer-deserializer) , which will enable design engineers to evaluate and develop transceiver links for high-bandwidth applications ranging from 600 Mbps to 12.5 Gbps. Users of the kit can verify compliance with popular communication protocol standards, including 10GbE, 10GBASE-KR, PCI Express® (PCIe®) Gen1, Gen2 and Gen3, Serial RapidIO®, Gigabit Ethernet (GbE), 10 GbE XAUI, CEI-6G, CEI-11G, HD-SDI, Interlaken and Fiber Channel.
The $4,995 kit includes the Stratix V GX development board (5SGXEA7N2F40C2NES) and a one-year license for the company's Quartus® II design software. Altera also provides design examples and access to their MegaCore® IP library, including the Nios® II Embedded Design Suite.
Features of the Stratix V kit include:
Configuration status and set-up elements:
JTAG
On-board USB Blaster
FPP configuration via MAX II device and flash memory
Two configuration file storage
Temperature measurement circuitry (Die & Ambient temperature)
The 2nd annual GLOBALFOUNDRIES Technology Conference (GTC), held in Santa Clara - CA on August 30, provided a rare opportunity to hear from leaders of each of the three largest EDA companies, along with the CEO of the largest semiconductor IP company, gathered together on the same stage to discuss a wide range of issues that will impact the future direction of the electronics design ecosystem.
Mojy Chian, the Senior VP for Design Enablement at GLOBALFOUNDRIES, moderated the panel discussion and presented a series of questions to the executives for nearly one-hour, followed by several questions from the audience.
The panel members:
Robert Hum, VP and GM, Mentor Graphics - Deep Submicron Division
Warren East, CEO of ARM Holdings plc
Lip-Bu Tan, CEO of Cadence Design Systems
Aart de Geus, CEO of Synopsys, Inc.
The EE Daily News has published a 20-page special report reviewing, in its entirety, the CEO/executive panel discussion at GTC 2011. The report includes an edited transcript of the one hour plus Q&A session, along with an analysis and summary of the key takeaways.
The report will provide valuable information to EDA users, competitors, EDA financial analysts, and managers of companies throughout the EDA/IP/manufacturing ecosystem.
Table of Contents:
Introduction
Cadence CEO Lip-Bu Tan says Google, Facebook, and Cisco will follow Apple into designing their own ICs.
Is there an opportunity for “ARM inside” branding to differentiate silicon IP, like “Intel inside” for PCs?
Synopsys CEO Aart de Geus says we are in a transition from Moore’s Law scale complexity to systemic complexity.
de Geus says that risk adds a 3rd dimension to design tradeoffs.
Mentor Graphics’ Robert Hum calls for deeper alliances and cooperation across the industry.
ARM’s CEO says no magic wands - concurrent development of tools, process and IP is critical.
Synopsys’ de Geus says a fundamental change has occurred at 28nm.
Complexity challenges: Aart says abstraction stack gets higher, Hum says analog is the “fly in the ointment”, Tan says “we all have to work more closely together”
GLOBALFOUNDRIES asks - Are there other things that EDA, the IP companies, and the foundries need to do together?
ARM’s CEO, citing example of Linaro, encourages reluctant EDA executives to see the value in horizontal collaboration.
EDA execs expound on why analog is so hard.
Audience question asks… how can EDA/IP get a bigger piece of the mobile industry pie?
Cadence’s Tan says customers want Groupon, in response to changing the EDA business model.
EDA execs on design in the cloud.
Summary
The report is available for purchase at $250 per copy. Simply click on the button below for secure payment through PayPal.
