Friday, June 3, 2011

DAC 2011 previews: Oasys Design Systems adds DFT to its Chip Synthesis™ platform.

Oasys Design Systems has announced the addition of DFT (design for test) capabilities to the company's Chip Synthesis™ platform. Oasys had previously announced support for chip-level power analysis and optimization, providing designers with the ability to synthesize a design from the RTL (register transfer level) with UPF (Unified Power Format) or CPF (Common Power Format) power constraints.

The company claims that these additional features complete a fully integrated Chip Synthesis front-to-back design flow. With RealTime Designer, you can perform "full-chip DFT synthesis in a single pass with fast turnaround and without the need for complex DFT abstraction and bottom-up flows", according to Oasys.

Chip Synthesis DFT features include design checking and debugging for rule violations, test clock analysis, power-domain aware physical scan chain ordering and lockup-latch insertion. Oasys has integrated a third-party DFT-compression capability is into the product.  You can also import information on pre-inserted DFT logic can in IEEE 1450.6 CTL (Core Test Language) format.

Availability and Pricing

Oasys is shipping RealTime Designer, with DFT and chip-level power analysis capabilities, now. The price for the product starts at $395,000 (U.S.) for a one-year, time-based license.

Oasys will offer demonstrations in Booth #2031 at the 48th Design Automation Conference (DAC) June 6-8 at the San Diego Convention Center in San Diego, Calif.

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