I was introduced to Marvell's "plug computer", and the Plug Computing Initiative, at last night's meeting of the Santa Clara Valley IEEE Consumer Electronics Society. Dr. Simon Milner, VP and General Manager of Marvel's Enterprise Business Unit gave an interesting (and entertaining) presentation.
So, if you're like me, you're probably asking "what the heck is a plug computer"? I will give you my impressions here, but you can also listen to the narrated slideshow at www.plugcomputer.org. That sounds like Dr. Milner doing the narration.
The plug computer is, as its name suggests (and as you can see from the pictures above), a fully functional computer with CPU, memory, and I/O - all contained within a form factor roughly the size of your typical (and unfortunately ubiquitous) power supply module. The processor is a customized ARM architecture. There are .5GB of RAM, and another .5GB of Flash, along with USB 2.0 and Ethernet ports. No on/off switch, just plug it in to your WiFI router and you've got a networked computer.
OK, but what would I do with such a thing (I asked myself)? Well, the first targeted application is to easily enable management of digital media on network attached-storage. So, add an external USB hard drive.
Then what you have, for only ~$100 plus the cost of the HDD, is a cheap & simple platform to provide access to digital media over your LAN or the internet. And... it's all available as an Open Source development kit. The way a consumer would buy this is with an application package pre-installed and configured by one of the Plug Computing Partners. Dr. Milner envisions something akin to the iPhone app store concept, and in fact one of the early OEMs, Cloud Engines, has developed an iPhone application for accessing their Pogoplug. The product description for Pogoplug:
Imagine accessing all your files and media at home from any laptop or desktop computer, anywhere in the world, or sharing this content with friends and family without having to upload. There's even an iPhone application so you can always "phone home" to get your files!
Hopefully, now you have some ideas for how this device would be used. I can see it stimulating other entrepreneurs to develop other applications. Here is a summary of my thoughts, pro & con.
Pro:
- Cheap, <$100.
- Very low power, ~2W.
- Easier than using your home PC as a media server.
- No firewall setup required.
- The whole world isn't as techie as silicon valley... it's still another box (or 2).
- Currently must be placed near your WiFI router.
As IEEE SV CES Chair Bill Orner noted, looking at something like the plug computer, it is amazing how far cheap computing power has come. I still think that for most consumers, managing a home wireless LAN is beyond their capability. However, once setup, it appears that adding devices like this to a network may be pretty painless. I could see a plug computer + storage, possibly Flash rather than HDD, built into some consumer electronics. We already see WiFI enabled devices like Blu-Ray players, and some new flat-panel TV sets.
-Mike
I just discovered that I may have accidentally deleted one of my previous posts, in which I offered a PDF copy of my 3 days of reports from the 46th Design Automaton Conference. I'm not sure how that happened, but I suspect it came about during a series of (painful) edits I experienced in order to make html tags work in the table of contents for my article on the DAC EDA CEO panel. I hope it wasn't a hack of some sort.
Since I had such a great response the 1st time, I will repeat the offer here. If you email me at michael.demler@digdia.com, I will send you a link to download your own copy of my 16 page report combining Day 1, Day 2 and Day 3 along with embedded Flash audio of the iPDK panel discussions - one of the highlights of this year's DAC. I have learned that you must use Adobe Acrobat Reader Version 9 to access the embedded audio, so make sure to download the latest version. Do not use the "Check for Updates" function on previous versions, since that will only get you the latest "dot" release.
-Mike
Since I had such a great response the 1st time, I will repeat the offer here. If you email me at michael.demler@digdia.com, I will send you a link to download your own copy of my 16 page report combining Day 1, Day 2 and Day 3 along with embedded Flash audio of the iPDK panel discussions - one of the highlights of this year's DAC. I have learned that you must use Adobe Acrobat Reader Version 9 to access the embedded audio, so make sure to download the latest version. Do not use the "Check for Updates" function on previous versions, since that will only get you the latest "dot" release.
-Mike
There have been several earlier reports and commentaries on the annual EDA CEO panel at DAC, but they are either strongly negative (Peggy Aycinena's "kill-me-now", Dan Nenni's "sleeping room only") or necessarily incomplete (Dylan McGrath and Nicolas Mokhoff at EETimes). It was a long session, and after listening to it a few times, as well as attending live, I see a lot of material that deserves more attention and discussion.
You can watch a video of the entire 1hr:15min discussion on the DAC website. Panel organizer professor Andrew Kahng also explains that he really was taking SMS messages on EDA Design Line. (That was a surprise, looked fake to me). Perhaps the "traditional" press may have seen the questions that were asked as "softballs", since they were not running the show. But I think there is value in hearing what the CEOs of Cadence, Mentor and Synopsys had to say, and that it is best gleaned by taking the time to break it all down.
Herein then, is my "random access" analysis of the DAC CEO panel. You can save time by going directly to any of the 15 questions that were asked during the panel.
PLEASE NOTE: To get the full benefit, you must be using the Firefox browser directly on my blog site. (Sorry, if IE is still your browser).
1.Introduction
2.What will be the impact of the economic downturn?
3.What are customer CEOs saying?
4.Innovation and venture capital investment in fabless companies
5.What advice do you have for EDA entrepreneurs?
6.How strong is the trend to customer consolidation?
7.Do you agree that EDA could get a larger share of semiconductor revenue?
8.Design services and silicon IP
9.Do you see EDA moving into automating design in other industries?
10.Is EDA addressing 3D?
11.What are you doing operationally to deal with market pressures?
12.What is being done to develop EDA talent?
13.How to keep students working on EDA problems?
14.What is the next silver bullet to have a substantial impact on design costs?
15.Closing comments
1. Introduction
Chair: Juan-Antonio Carballo - IBM Corp.
Panelists:
Aart de Geus - Synopsys, Inc.
Walden C. Rhines - Mentor Graphics Corp.
Lip-Bu Tan - Cadence Design Systems, Inc.
Top
2. What will be the impact of the economic downturn?
Wally: Had 1st year of "negative growth" in EDA. It is a period of opportunity.
Lip-Bu: Getting closer to customers to help them lower design costs.
Aart: This one feels different, a "reset" of global standard of living. The impact is that all of EDA, hi-tech, and semiconductor will be about increasing efficiency. EDA is facing either a "massive squeeze" or a "massive opportunity".
My comments: While the CEOs attempted to to be upbeat for the most part, there is still a lot of uncertainty. Aart was the most realistic, putting the impact of the economic meltdown on EDA into a broader perspective. He even questioned Juan-Antonio on his "optimistic" assessment.
Keep in mind that the "we" represented here is just the big-3 of EDA. Smaller, less diversified EDA companies are suffering more. Aart pointed to consolidation of manufacturing in the semiconductor industry as an example of increasing efficiencies. The same rule must hold for the EDA industry as well. We can expect consolidation through attrition, more than acquisition, to eliminate redundant products and weaker companies.
Top
3. What are customer CEOs saying?
Aart: We now get access to CEOs, who are calling for help through lower pricing. This is an opportunity to treat endemic problems. i.e. the overall cost of design.
Lip-Bu: Reducing time-to-market and design cost are critical. Building ecosystem of partners, helping more through IP and services so that customers can concentrate on core competencies.
Wally: Cost of EDA software has stayed same at a constant percentage of semiconductor revenue. Cost of system design is the issue. EDA has opportunity to deal with the "whole problem".
My comments: Economic leverage resides in the customers, who will continue to apply economic pressures on their vendors, even more so than in the past. The holistic view, which came up again later, is the right one to have. The question is, are the major EDA vendors willing to structure their operations to address the "whole problem", instead of the current structure of individual business units focused just their piece of the problem?
Top
4. Innovation and venture capital investment in fabless companies.
Lip-Bu: Investment is declining substantially, down 70%. Average investment required is $75-$100M but average exit is only $55-$60M, so just can't make money. Hoping for "up & coming" (e.g. nVidia) companies that will buy more tools.
Aart: One of the things startups have is no legacy, so they can start on a new design methodology from the outset.
Wally: Still sees "lots of companies" started, but more in analog and RF. The fact that more companies are fabless or fab-light increases opportunity for EDA.
My comments: Lip-Bu mentioned that "we all have a role to play". That notion would align with TSMC's "community business model", but are all the players willing to cooperate to make that happen?
Aart mentioned the need to limit the degrees of freedom in design, in order to keep costs under control, which I interpret as a more IP-based design methodology. This would align well with Synopsys' IP business.
Wally's comment on seeing more analog and RF startups is interesting. This should be an opportunity for more innovation in analog EDA, which is likely to come more from EDA startups.
Top
5. What advice do you have for EDA entrepreneurs?
Lip-Bu: "Find a real tough problem and try to solve it" and "listen to the customer". Opportunities in higher level of abstraction, low power, DFM. "Partner with one of us".
Wally: "Don't run out of money". Much of EDA is a mature market, almost all growth over last 10 years has been from DFM, ESL, some analog/RF. Look at things that big companies overlook.
Aart: Been watching with increased worry that startups are too focused on doing something incremental to get bought out. Need to work on something that has bigger impact than incremental.
My comments: In a reversal of the "preferred vendor" sales strategy of recent years, Lip-Bu pointed out that many companies don't want to work with a single vendor, leaving opportunities for point tools. In regards to Aart's comment on the quick-exit mindset in startups, doesn't EDA have to take a lot of the blame for the innovation through acquisition strategies of the past? I do agree though, EDA entrepreneurs must focus on being profitable and differentiated because the exit strategies of the past no longer exist.
Top
6. How strong is the trend to customer consolidation?
Aart: Now seeing attrition through bankruptcies. Thinks we will see a third wave later this year or next year, since the recession will go on for a while.
Wally: Customers are consolidating manufacturing but not total number of companies. Market share does not change, but the names of the companies do.
Lip-Bu: Overall, consolidation is good to get companies to focus on core competencies.
My comments: All of the comments point to further contraction in the EDA industry.
Top
7. Do you agree that EDA could get a larger share of semiconductor revenue? (Or.. are you getting an unfair share?)
Aart: That's a "b.s." question. There is an opportunity to get more share, but only on the basis of an economic push. "There has to be a massive focus on productivity. "
Wally: For EDA to get more means that someone else must get less. Other opportunity is in other industries; such as automotive and aerospace.
Lip-Bu: Huge opportunity in the increased amount of verification and debugging required, system-level, and combined analog/mixed-signal in SoCs will be be "really big".
My comments: It should be obvious that EDA revenues will not reverse their decline while semiconductor revenues continue to decrease. (Aart estimated -25% for semis this year). This again points to further contraction in EDA. Moving into adjacent industries and offering more comprehensive solutions are potential long-term strategies, but are not likely to change the economics in the near-term. CAD tools for the automotive and aerospace industries are nothing new. Take a look at Autodesk, which is older and larger than any EDA company.
Top
8. Design services and silicon IP
Lip-Bu: Sees "tremendous growth" in design services.
Wally: IP increasing as percent of TAM for the industry. EDA can provide services better than anyone else. Growth of software will match growth of services.
Aart: IP is not a "thing", part of a design methodology, a gradual evolution to assembly of building blocks.
My comments: Interesting that Aart focused on IP while the other CEOs focused on services. His comments on the building-block approach go along with his answers to the 4th question. The Synopsys vision is one where what was once board-level design is now a system-on-a-chip. The IP play is one way to participate in that paradigm shift, and it is actually a lot easier than building a "whole-chip" solution . In the past, there were concerns that EDA companies (and foundries) developing IP would be competing with their customers. Economics and scale complexity may have changed that.
Top
9. Do you see EDA moving into automating design in other industries?
Wally: Great opportunity for EDA in adjacent industries. Almost an "unlimited opportunity".
Lip-Bu: Medical research industry can be an interesting opportunity.
Aart: Challenge is to be specific. "Grass always looks so much greener", not that easy. Opportunities are in immediate adjacencies, power is a big spectrum of issues.
My comments: I was in EDA for fifteen years, so I know this won't be the first time someone speculated on this, but it would be more likely for a system CAD company to move down to EDA than for EDA to try to move up. On this question, I also thought that Aart had the most realistic answer. EDA companies will only be able to branch out through very close partnering with customers. New ventures would likely be required, whether to address power or other problems. Once again, see the TSMC community-based business model.
Top
10. Is EDA addressing 3D?
Wally: Hot area now, but customers probably won't be willing to pay a premium. Will need 3D packaging to move beyond Moore's Law.
Lip-Bu: Cadence is a "leader in System on a Chip packaging". Heavily engaging with customers.
Aart: 3D is not new. What is most intriguing is changing type of components in the stack; FPGAs, MEMs, etc. Impact on yield is a problem.
My comments: Aart is right, 3D is not new. I recall more than twenty years ago when the U.S. Defense Dept. was funding research for a massively parallel computer. "Massively paralllel" in those days meant physically parallel - stacking multiple processors in a single package. Sound familiar? What was once radical thinking will become more mainstream, but it's also no different than SiP or MCMs. EDA did not do too much there because the problems are mechanical as well as electrical, not exactly their forte. This is a potential growth area however.
Top
11. What are you doing operationally to deal with market pressures?
Wally: "I'm flying coach".
Lip-Bu: Run Cadence like a startup.
Aart: "I serve snacks to Wally". Helping customers survive.
My comments: Once again, as at DvCon, nobody wanted to use the "L word".
Top
12. What is being done to develop EDA talent?
Wally: Single most important thing we do. Finding talent wherever it is.
Aart: Management does not have answers on right things to do. Thinks there is nothing more motivating than working on problems in difficult times. Retain employees who care about the company mission.
Lip-Bu: Create a culture of "sticking together" on shared mission.
My comments: Interesting emphasis on off-shoring, or globalization, by Wally. Aart referred to intellectual rewards to make up for loss of economic rewards, and was finally the first CEO to mention not retaining some employees if they can't "embrace the company mission".
Top
13. How to keep students working on EDA problems?
Aart: Start before university level. Need to keep kids in school. More important to be well-rounded.
Lip-Bu: U.S. needs more engineers.
Wally: The Semiconductor Research Corporation (SRC) allocates half of their funding to design-related research.
My comments: I don't know anybody that got a degree in EDA, so Aart was right to point to the larger issue of math and science education. Otherwise, this was a silly question. Students don't generally work on EDA problems until they are in grad school. With the large (unspoken here) number of EDA layoffs that have occurred, there is a sound economic reason that students may not pursue an EDA career.
Top
14. What is the next silver bullet to have a substantial impact on design costs?
Aart: Problem is now systemic complexity. Need more people who can see how entire design flow works together.
Lip-Bu: No silver bullets, repeated need for verification and system-level solutions.
Wally: Improvements needed in all phases of design. Look at system end of design where costs are growing, especially embedded software.
My comments: Most interesting to me was Aart's comment that there is an "awesome opportunity" for people who can understand and see multiple aspects of the design problem, and "how to make the entire design flow work together".
At DAC, I was reminded by an old friend from my Cadence days what a great accomplishment it was that we had built an actual, working, top-to-bottom, AMS reference flow. We put a prototype design through it and made sure that perhaps a dozen or more analog and digital tools worked together. We had mixed-signal circuits, IP, we had a memory block, we had synthesized logic... just about all the elements you would see in an SoC today. It was never meant to be productized (though an attempt was made and it failed), it was meant to show that we could address the entire flow.
The most important element, that I think is still lacking in EDA, is structuring the businesses around the flow and not around the point tools. That is the problem that needs to be solved today, especially when you look at incorporating system-level design. At DAC, during Hogan's Heroes pavilion panel, there was even a mention of variability being a problem at system level.
But EDA companies reward individual business units and product lines. Who owns the whole flow, including analog and digital? Will any EDA company structure themselves to address the whole-chip problem?
Top
15. Closing comments
Aart: At a crossroads moment, where success is a global challenge. Technology is the only way we can address some of the problems.
Lip-Bu: Recovery is on the horizon. New technology and consumer products need EDA.
Wally: Electronics industry is unique in ability to respond to economic disruptions. Predicts that next year at this time we will report a growth quarter for EDA.
My comments: The concluding optimistic remarks were not entirely consistent with the earlier discussions. EDA may begin an upward trend one year from now, but how much more contraction and attrition will occur before that happens?
Top
You can watch a video of the entire 1hr:15min discussion on the DAC website. Panel organizer professor Andrew Kahng also explains that he really was taking SMS messages on EDA Design Line. (That was a surprise, looked fake to me). Perhaps the "traditional" press may have seen the questions that were asked as "softballs", since they were not running the show. But I think there is value in hearing what the CEOs of Cadence, Mentor and Synopsys had to say, and that it is best gleaned by taking the time to break it all down.
Herein then, is my "random access" analysis of the DAC CEO panel. You can save time by going directly to any of the 15 questions that were asked during the panel.
PLEASE NOTE: To get the full benefit, you must be using the Firefox browser directly on my blog site. (Sorry, if IE is still your browser).
1.Introduction
2.What will be the impact of the economic downturn?
3.What are customer CEOs saying?
4.Innovation and venture capital investment in fabless companies
5.What advice do you have for EDA entrepreneurs?
6.How strong is the trend to customer consolidation?
7.Do you agree that EDA could get a larger share of semiconductor revenue?
8.Design services and silicon IP
9.Do you see EDA moving into automating design in other industries?
10.Is EDA addressing 3D?
11.What are you doing operationally to deal with market pressures?
12.What is being done to develop EDA talent?
13.How to keep students working on EDA problems?
14.What is the next silver bullet to have a substantial impact on design costs?
15.Closing comments
1. Introduction
Chair: Juan-Antonio Carballo - IBM Corp.
Panelists:
Aart de Geus - Synopsys, Inc.
Walden C. Rhines - Mentor Graphics Corp.
Lip-Bu Tan - Cadence Design Systems, Inc.
Top
2. What will be the impact of the economic downturn?
Wally: Had 1st year of "negative growth" in EDA. It is a period of opportunity.
Lip-Bu: Getting closer to customers to help them lower design costs.
Aart: This one feels different, a "reset" of global standard of living. The impact is that all of EDA, hi-tech, and semiconductor will be about increasing efficiency. EDA is facing either a "massive squeeze" or a "massive opportunity".
My comments: While the CEOs attempted to to be upbeat for the most part, there is still a lot of uncertainty. Aart was the most realistic, putting the impact of the economic meltdown on EDA into a broader perspective. He even questioned Juan-Antonio on his "optimistic" assessment.
Keep in mind that the "we" represented here is just the big-3 of EDA. Smaller, less diversified EDA companies are suffering more. Aart pointed to consolidation of manufacturing in the semiconductor industry as an example of increasing efficiencies. The same rule must hold for the EDA industry as well. We can expect consolidation through attrition, more than acquisition, to eliminate redundant products and weaker companies.
Top
3. What are customer CEOs saying?
Aart: We now get access to CEOs, who are calling for help through lower pricing. This is an opportunity to treat endemic problems. i.e. the overall cost of design.
Lip-Bu: Reducing time-to-market and design cost are critical. Building ecosystem of partners, helping more through IP and services so that customers can concentrate on core competencies.
Wally: Cost of EDA software has stayed same at a constant percentage of semiconductor revenue. Cost of system design is the issue. EDA has opportunity to deal with the "whole problem".
My comments: Economic leverage resides in the customers, who will continue to apply economic pressures on their vendors, even more so than in the past. The holistic view, which came up again later, is the right one to have. The question is, are the major EDA vendors willing to structure their operations to address the "whole problem", instead of the current structure of individual business units focused just their piece of the problem?
Top
4. Innovation and venture capital investment in fabless companies.
Lip-Bu: Investment is declining substantially, down 70%. Average investment required is $75-$100M but average exit is only $55-$60M, so just can't make money. Hoping for "up & coming" (e.g. nVidia) companies that will buy more tools.
Aart: One of the things startups have is no legacy, so they can start on a new design methodology from the outset.
Wally: Still sees "lots of companies" started, but more in analog and RF. The fact that more companies are fabless or fab-light increases opportunity for EDA.
My comments: Lip-Bu mentioned that "we all have a role to play". That notion would align with TSMC's "community business model", but are all the players willing to cooperate to make that happen?
Aart mentioned the need to limit the degrees of freedom in design, in order to keep costs under control, which I interpret as a more IP-based design methodology. This would align well with Synopsys' IP business.
Wally's comment on seeing more analog and RF startups is interesting. This should be an opportunity for more innovation in analog EDA, which is likely to come more from EDA startups.
Top
5. What advice do you have for EDA entrepreneurs?
Lip-Bu: "Find a real tough problem and try to solve it" and "listen to the customer". Opportunities in higher level of abstraction, low power, DFM. "Partner with one of us".
Wally: "Don't run out of money". Much of EDA is a mature market, almost all growth over last 10 years has been from DFM, ESL, some analog/RF. Look at things that big companies overlook.
Aart: Been watching with increased worry that startups are too focused on doing something incremental to get bought out. Need to work on something that has bigger impact than incremental.
My comments: In a reversal of the "preferred vendor" sales strategy of recent years, Lip-Bu pointed out that many companies don't want to work with a single vendor, leaving opportunities for point tools. In regards to Aart's comment on the quick-exit mindset in startups, doesn't EDA have to take a lot of the blame for the innovation through acquisition strategies of the past? I do agree though, EDA entrepreneurs must focus on being profitable and differentiated because the exit strategies of the past no longer exist.
Top
6. How strong is the trend to customer consolidation?
Aart: Now seeing attrition through bankruptcies. Thinks we will see a third wave later this year or next year, since the recession will go on for a while.
Wally: Customers are consolidating manufacturing but not total number of companies. Market share does not change, but the names of the companies do.
Lip-Bu: Overall, consolidation is good to get companies to focus on core competencies.
My comments: All of the comments point to further contraction in the EDA industry.
Top
7. Do you agree that EDA could get a larger share of semiconductor revenue? (Or.. are you getting an unfair share?)
Aart: That's a "b.s." question. There is an opportunity to get more share, but only on the basis of an economic push. "There has to be a massive focus on productivity. "
Wally: For EDA to get more means that someone else must get less. Other opportunity is in other industries; such as automotive and aerospace.
Lip-Bu: Huge opportunity in the increased amount of verification and debugging required, system-level, and combined analog/mixed-signal in SoCs will be be "really big".
My comments: It should be obvious that EDA revenues will not reverse their decline while semiconductor revenues continue to decrease. (Aart estimated -25% for semis this year). This again points to further contraction in EDA. Moving into adjacent industries and offering more comprehensive solutions are potential long-term strategies, but are not likely to change the economics in the near-term. CAD tools for the automotive and aerospace industries are nothing new. Take a look at Autodesk, which is older and larger than any EDA company.
Top
8. Design services and silicon IP
Lip-Bu: Sees "tremendous growth" in design services.
Wally: IP increasing as percent of TAM for the industry. EDA can provide services better than anyone else. Growth of software will match growth of services.
Aart: IP is not a "thing", part of a design methodology, a gradual evolution to assembly of building blocks.
My comments: Interesting that Aart focused on IP while the other CEOs focused on services. His comments on the building-block approach go along with his answers to the 4th question. The Synopsys vision is one where what was once board-level design is now a system-on-a-chip. The IP play is one way to participate in that paradigm shift, and it is actually a lot easier than building a "whole-chip" solution . In the past, there were concerns that EDA companies (and foundries) developing IP would be competing with their customers. Economics and scale complexity may have changed that.
Top
9. Do you see EDA moving into automating design in other industries?
Wally: Great opportunity for EDA in adjacent industries. Almost an "unlimited opportunity".
Lip-Bu: Medical research industry can be an interesting opportunity.
Aart: Challenge is to be specific. "Grass always looks so much greener", not that easy. Opportunities are in immediate adjacencies, power is a big spectrum of issues.
My comments: I was in EDA for fifteen years, so I know this won't be the first time someone speculated on this, but it would be more likely for a system CAD company to move down to EDA than for EDA to try to move up. On this question, I also thought that Aart had the most realistic answer. EDA companies will only be able to branch out through very close partnering with customers. New ventures would likely be required, whether to address power or other problems. Once again, see the TSMC community-based business model.
Top
10. Is EDA addressing 3D?
Wally: Hot area now, but customers probably won't be willing to pay a premium. Will need 3D packaging to move beyond Moore's Law.
Lip-Bu: Cadence is a "leader in System on a Chip packaging". Heavily engaging with customers.
Aart: 3D is not new. What is most intriguing is changing type of components in the stack; FPGAs, MEMs, etc. Impact on yield is a problem.
My comments: Aart is right, 3D is not new. I recall more than twenty years ago when the U.S. Defense Dept. was funding research for a massively parallel computer. "Massively paralllel" in those days meant physically parallel - stacking multiple processors in a single package. Sound familiar? What was once radical thinking will become more mainstream, but it's also no different than SiP or MCMs. EDA did not do too much there because the problems are mechanical as well as electrical, not exactly their forte. This is a potential growth area however.
Top
11. What are you doing operationally to deal with market pressures?
Wally: "I'm flying coach".
Lip-Bu: Run Cadence like a startup.
Aart: "I serve snacks to Wally". Helping customers survive.
My comments: Once again, as at DvCon, nobody wanted to use the "L word".
Top
12. What is being done to develop EDA talent?
Wally: Single most important thing we do. Finding talent wherever it is.
Aart: Management does not have answers on right things to do. Thinks there is nothing more motivating than working on problems in difficult times. Retain employees who care about the company mission.
Lip-Bu: Create a culture of "sticking together" on shared mission.
My comments: Interesting emphasis on off-shoring, or globalization, by Wally. Aart referred to intellectual rewards to make up for loss of economic rewards, and was finally the first CEO to mention not retaining some employees if they can't "embrace the company mission".
Top
13. How to keep students working on EDA problems?
Aart: Start before university level. Need to keep kids in school. More important to be well-rounded.
Lip-Bu: U.S. needs more engineers.
Wally: The Semiconductor Research Corporation (SRC) allocates half of their funding to design-related research.
My comments: I don't know anybody that got a degree in EDA, so Aart was right to point to the larger issue of math and science education. Otherwise, this was a silly question. Students don't generally work on EDA problems until they are in grad school. With the large (unspoken here) number of EDA layoffs that have occurred, there is a sound economic reason that students may not pursue an EDA career.
Top
14. What is the next silver bullet to have a substantial impact on design costs?
Aart: Problem is now systemic complexity. Need more people who can see how entire design flow works together.
Lip-Bu: No silver bullets, repeated need for verification and system-level solutions.
Wally: Improvements needed in all phases of design. Look at system end of design where costs are growing, especially embedded software.
My comments: Most interesting to me was Aart's comment that there is an "awesome opportunity" for people who can understand and see multiple aspects of the design problem, and "how to make the entire design flow work together".
At DAC, I was reminded by an old friend from my Cadence days what a great accomplishment it was that we had built an actual, working, top-to-bottom, AMS reference flow. We put a prototype design through it and made sure that perhaps a dozen or more analog and digital tools worked together. We had mixed-signal circuits, IP, we had a memory block, we had synthesized logic... just about all the elements you would see in an SoC today. It was never meant to be productized (though an attempt was made and it failed), it was meant to show that we could address the entire flow.
The most important element, that I think is still lacking in EDA, is structuring the businesses around the flow and not around the point tools. That is the problem that needs to be solved today, especially when you look at incorporating system-level design. At DAC, during Hogan's Heroes pavilion panel, there was even a mention of variability being a problem at system level.
But EDA companies reward individual business units and product lines. Who owns the whole flow, including analog and digital? Will any EDA company structure themselves to address the whole-chip problem?
Top
15. Closing comments
Aart: At a crossroads moment, where success is a global challenge. Technology is the only way we can address some of the problems.
Lip-Bu: Recovery is on the horizon. New technology and consumer products need EDA.
Wally: Electronics industry is unique in ability to respond to economic disruptions. Predicts that next year at this time we will report a growth quarter for EDA.
My comments: The concluding optimistic remarks were not entirely consistent with the earlier discussions. EDA may begin an upward trend one year from now, but how much more contraction and attrition will occur before that happens?
Top
This is my third (and last) daily agenda review from the 46th Design Automation Conference (DAC).
(If you are an email subscriber and did not see the embedded audio player in my Day 2 report, you will need to go to the-world-is-analog.blogspot.com to listen to the iPDK debate.)
Wednesday - Day 3
1. Meeting with Mephisto Design Automation
Mephisto is another recent entrant into the latest generation of analog optimization vendors. In the last generation there was Neolinear, Antrim, Analog Design Automation, Barcelona... now we have Magma, Mephisto, MunEDA, Orora, Ansyn... There just wasn't time to see them all.
I was interested to check out Mephisto, since they are attempting to commercialize technology developed under Prof. Georges Gielen at KU Leuven in Belgium. Georges was an adviser to us at Antrim, and I enjoyed visiting with his students on several occasions. Unfortunately, after another early morning drive to San Francisco, this meeting never happened as I found myself standing in an empty booth. You've got to get more organized guys!
So, I can only attempt to interpret the product descriptions on Mephisto's website. They claim to be able to do "sizing from scratch", which is a more aggressive claim than most competitors. It is very difficult and inefficient, and often impossible, to start an optimization with a completely un-parameterized circuit. We patented methods to address this at Antrim. It actually appears that their technology for verification is more valuable than the tools for optimization.
Mephisto also claims to have "patent-pending technology" (couldn't find any pending claims on http://www.blogger.com/www.upsto.gov) that "allows designers to capture and solve complex design problems at multiple abstraction levels simultaneously". This is also something we developed at Antrim, to move beyond brute-force SPICE simulation-based optimization algorithms. To avert any potential conflict, I advise checking out the Antrim patents, which now belong to Cadence,
2. Meeting with Tanner EDA
With analog design tools currently splitting into the IPL/OA-based camp (Synopsys, Springsoft, Ciranova, Analog Rails) or Cadence, I was interested to get the perspective of twenty-year old Tanner, which has long been the budget-minded alternative. In fact, Tanner emphasized how much cheaper they are in their booth presentation of an "ROI calculator".
I met with Daniel Hamon, VP and General Manager, who began with a review of Tanner's history as the EDA division of Tanner Research. Tanner EDA has 25,000 installed seats, a significant number compared to what I recall of Cadence's installed base. Their tools are primarily used on Windows-based PCs.
Tanner has not joined the Open Access movement, but Daniel Hamon emphasized the interoperability built into their toolset. Tanner's customer base of analog/RF designers are generally doing much smaller high-performance designs, which require dedicated analog processes rather than nanometer CMOS. Tanner does support TSMC processes at 0.35um-0.18um, and also has design kits for X-fab, Austria Microsystems, and MOSIS.
3. Meeting with Silicon Frontline
Silicon Frontline was formed by a team from Nassda that had developed the advanced post-layout analysis capabilities which set HSIMplus apart form other Fast-SPICE solutions. I know, because I emphasized and promoted that differentiation while I was the product marketing manager. It is a differentiation which Synopsys still gets to enjoy today.
I met with Dermott Lynch, Silicon Frontline's VP of Sales, to discuss the company's new solutions for 3D extraction (which made Gary Smith's "What to See" at DAC list). The company claims to provide near-3D RC extraction accuracy with something approaching 2D performance. Rather than go into a great amount of detail here, I will direct you to an extensive interview with Yuri Feinberg and Andrei Tcherniaev that is available at SCDsource. The cumulative experience of the ex-Nassda team in how to manage large parasitic databases, and to optimize analysis of effects in signal and power nets, does make them a company to watch.
4. Meeting with Ansyn
Ansyn was the 3rd analog optimization company on my agenda, catching my eye for their claim to perform "Analog Circuit Synthesis at System Level". This was the company's 1st time at DAC, after spinning off technology developed at Linköping University in Sweden in 2006. I met with Emil Hjalmarson, PhD and CEO of the new startup.
The discussion with Ansyn turned out to be, totally by chance, the highlight of DAC for me. As I was discussing Ansyn's approach to simulation-based optimization with Emil, I could not see behind me as a gentleman apologized for interrupting as he grabbed some literature from the rack in the corner of the tiny booth. Emil appeared to be especially concerned about who the stranger was, as he asked us if we minded him listening in to our conversation. The stranger then identified himself - "I'm Andrei Vladimirescu", he said. If you know SPICE, you know Prof. Andrei Vladimirescu, since he co-wrote the 1st successful version: SPICE-2. He is also the author of "The SPICE Book".
This made for a very stimulating impromptu conversation as we discussed the pros and cons of integrating an optimizer into the core of a new simulator, as Ansyn has chosen to do. We debated this very same issue when we were developing our product plan at Antrim. Prof. Vladimirescu rightly pointed out that achieving market acceptance and foundry endorsement for a new simulator is a major challenge, and can be an insurmountable obstacle to success. On the other hand, having the optimizer wrapped around an existing commercial simulator means suffering huge performance penalties.
At Antrim, I had argued for the deeply embedded approach, so that we could build a revolutionary system that would be designed not so much for simulation as for optimization, by allowing the "synthesizer" to directly alter the matrix dynamically. Well, R&D would have none of that, and instead we ended up building the worst of both worlds. We had a new proprietary simulator AND, in order to accelerate that development as a stand-alone product, we still wrapped the optimizer around the outside.
For optimization, Ansyn's tool can potentially achieve higher performance than other solutions. They are also taking advantage of mutli-core processing, which has become popular for accelerating traditional SPICE simulators. I don't see any realization at this point to back up the provocative "synthesis" claim, but it will we interesting to see if Ansyn comes away from their 1st DAC visit with a desire to jump into the EDA fray, or stay local in the much smaller European market.
5. Follow-up Discussion with CoWare on modeling and simulation of next generation LTE modems
Following on my introduction to CoWare's LTE modem solution on Tuesday at DAC, I had the opportunity to sit down for a chat with Dr. Johannes Stahl, VP Marketing & Business Development. CoWare has addressed the concept of virtual platforms with a vertical market solution for the 4G mobile wireless market.
As a bit of background; the 4th generation (or 4G) of wireless technology will be characterized by a flat end-to-end internet protocol (IP) network that is optimized for broadband data communications. This is a very significant change as all preceding generations, including today's 3G, are based on (what is at best) a hybrid architecture that was optimized for voice from the outset. A partisan debate between advocates of two similar technologies for the radio access part of 4G networks, mobile WiMAX and LTE, has detracted from the development. As things stand today, mobile WiMAX has been deployed in several U.S. cities by Clearwire/Sprint, while LTE is yet to begin its first field trials. (For much more on this, see my report "The Emerging 4G Wireless Landscape in the U.S.").
With LTE being several years behind WiMAX in regards to SoC development and network deployment, a virtual platform to accelerate software and algorithm development is essential. At a Santa Clara Valley IEEE Communication Society meeting earlier this year, representatives of several WiMAX chip providers emphasized that the algorithms are the critical element to wireless performance, more thanthe silicon. Chip complexity is increasing, as RF front ends are integrated into single-chip SoCs to lower cost, size, and power.
CoWare was very effective in utilizing Twitter to publicize the LTE presentations in their booth:
6. PAVILION PANEL: The AMS Revival: Bipolar Thinking?
Chair: Dave Maliniak - Electronic Design, New York, NY
Panelists:
Christoph Grimm - Technische Univ. Wien, Vienna, Austria
Mike Woodward - The MathWorks, Inc., Natick, MA
David Smith - Synopsys, Inc., Hillsboro, OR
This panel produced my favorite quote at DAC, from David Smith: "AMS is the whole world!". Yes, The World Is Analog!
So, if you've followed my blogs for a while, you will know that it is a continuing source of annoyance to see how analog is treated by the "non-cognoscenti". At this year's DAC, we already had analog referred to as "stodgy" and now in need of a "revival" and "bipolar"? Very funny. We all know that only digital types can be truly bi-polar ;-)
The discussion here was intended as a forum on the application of higher-level AMS design languages, such as System-C/AMS. Hence no designers on the panel? I had to stifle a laugh when one of the panelists said that it is "up to management to convince designers" to use top down methodologies. Riiight... let me know how that goes for you.
The thing is, to the extent it exists, analog designers already work top-down. It's just that, like every aspect of analog design, it's hard for the non-cognoscenti to understand because it doesn't look like digital - and it never will. With Mathworks, the provider of MATLAB, on the panel that should have gone without saying. Designers often use MATLAB to do early, high-level architectural analysis. At companies that are large enough to staff CAD and library groups, AMS behavioral modeling is commonly used as well, in Verilog-AMS or VHDL-AMS.
As just about everyone knows, the biggest difference between analog and digital is that there is no automated algorithmic top-down analog synthesis - it's mostly manual. That is unlikely to change anytime soon. However, what the non-cognoscenti also forget or ignore, is that there is plenty of "bottom-up" design that has to occur in digital as well, before you can execute your synthesis flow. Those cell libraries don't just materialize out of nowhere.
Mixed-signal IP is also employed extensively in AMS SoCs, same as in digital. It's just that most analog specifications require tuning and optimization, which is - by the way - why the highest performance digital chips are custom as well.
One of the panelists stated the opinion that new tools & languages are not required, that all you need is methodology and management. Other panels, such as the one following this session, differed with that opinion. Speakers at the Tuesday morning AMS breakfast had already shown some of the limitations of currently available tools for AMS verification, which was correctly identified as the #1 problem in AMS design.
It would be valuable to extend some digital verification concepts to AMS, especially the concept of assertions. I was an early participant in the Accelera Requirements Definition Working Group, where we explored how Verilog-AMS and System Verilog might be integrated to address this need. I am concerned though, that these committees often end up focusing more on defining a language than on defining a solution to the real problems.
7. PANEL: Guess, Solder, Measure, Repeat – How Do I Get My Mixed-Signal Chip Right?
Chair: Ken Kundert - Designer’s Guide Consulting, Los Altos, CA
Panelists:
Georges Gielen - Katholieke Univ. Leuven, Leuven, Belgium
Martin O’Leary - Cadence Design Systems, Inc., San Jose, CA
Eric Grimme - Intel Corp., Hillsboro, OR
Sandeep Tare - Texas Instruments, Inc., Dallas, TX
Warren Wong - Synopsys, Inc., Mountain View, CA
I was happy to hear Prof. Gielen say that they still require their students to learn to solder and measure. Nobody should be granted a EE degree without ever actually building something.
No new ground was covered here, but as my final session at DAC it was a good wrapup on AMS issues.
-Mike
(If you are an email subscriber and did not see the embedded audio player in my Day 2 report, you will need to go to the-world-is-analog.blogspot.com to listen to the iPDK debate.)
Wednesday - Day 3
1. Meeting with Mephisto Design Automation
Mephisto is another recent entrant into the latest generation of analog optimization vendors. In the last generation there was Neolinear, Antrim, Analog Design Automation, Barcelona... now we have Magma, Mephisto, MunEDA, Orora, Ansyn... There just wasn't time to see them all.
I was interested to check out Mephisto, since they are attempting to commercialize technology developed under Prof. Georges Gielen at KU Leuven in Belgium. Georges was an adviser to us at Antrim, and I enjoyed visiting with his students on several occasions. Unfortunately, after another early morning drive to San Francisco, this meeting never happened as I found myself standing in an empty booth. You've got to get more organized guys!
So, I can only attempt to interpret the product descriptions on Mephisto's website. They claim to be able to do "sizing from scratch", which is a more aggressive claim than most competitors. It is very difficult and inefficient, and often impossible, to start an optimization with a completely un-parameterized circuit. We patented methods to address this at Antrim. It actually appears that their technology for verification is more valuable than the tools for optimization.
Mephisto also claims to have "patent-pending technology" (couldn't find any pending claims on http://www.blogger.com/www.upsto.gov) that "allows designers to capture and solve complex design problems at multiple abstraction levels simultaneously". This is also something we developed at Antrim, to move beyond brute-force SPICE simulation-based optimization algorithms. To avert any potential conflict, I advise checking out the Antrim patents, which now belong to Cadence,
2. Meeting with Tanner EDA
With analog design tools currently splitting into the IPL/OA-based camp (Synopsys, Springsoft, Ciranova, Analog Rails) or Cadence, I was interested to get the perspective of twenty-year old Tanner, which has long been the budget-minded alternative. In fact, Tanner emphasized how much cheaper they are in their booth presentation of an "ROI calculator".
I met with Daniel Hamon, VP and General Manager, who began with a review of Tanner's history as the EDA division of Tanner Research. Tanner EDA has 25,000 installed seats, a significant number compared to what I recall of Cadence's installed base. Their tools are primarily used on Windows-based PCs.
Tanner has not joined the Open Access movement, but Daniel Hamon emphasized the interoperability built into their toolset. Tanner's customer base of analog/RF designers are generally doing much smaller high-performance designs, which require dedicated analog processes rather than nanometer CMOS. Tanner does support TSMC processes at 0.35um-0.18um, and also has design kits for X-fab, Austria Microsystems, and MOSIS.
3. Meeting with Silicon Frontline
Silicon Frontline was formed by a team from Nassda that had developed the advanced post-layout analysis capabilities which set HSIMplus apart form other Fast-SPICE solutions. I know, because I emphasized and promoted that differentiation while I was the product marketing manager. It is a differentiation which Synopsys still gets to enjoy today.
I met with Dermott Lynch, Silicon Frontline's VP of Sales, to discuss the company's new solutions for 3D extraction (which made Gary Smith's "What to See" at DAC list). The company claims to provide near-3D RC extraction accuracy with something approaching 2D performance. Rather than go into a great amount of detail here, I will direct you to an extensive interview with Yuri Feinberg and Andrei Tcherniaev that is available at SCDsource. The cumulative experience of the ex-Nassda team in how to manage large parasitic databases, and to optimize analysis of effects in signal and power nets, does make them a company to watch.
4. Meeting with Ansyn
Ansyn was the 3rd analog optimization company on my agenda, catching my eye for their claim to perform "Analog Circuit Synthesis at System Level". This was the company's 1st time at DAC, after spinning off technology developed at Linköping University in Sweden in 2006. I met with Emil Hjalmarson, PhD and CEO of the new startup.
The discussion with Ansyn turned out to be, totally by chance, the highlight of DAC for me. As I was discussing Ansyn's approach to simulation-based optimization with Emil, I could not see behind me as a gentleman apologized for interrupting as he grabbed some literature from the rack in the corner of the tiny booth. Emil appeared to be especially concerned about who the stranger was, as he asked us if we minded him listening in to our conversation. The stranger then identified himself - "I'm Andrei Vladimirescu", he said. If you know SPICE, you know Prof. Andrei Vladimirescu, since he co-wrote the 1st successful version: SPICE-2. He is also the author of "The SPICE Book".
This made for a very stimulating impromptu conversation as we discussed the pros and cons of integrating an optimizer into the core of a new simulator, as Ansyn has chosen to do. We debated this very same issue when we were developing our product plan at Antrim. Prof. Vladimirescu rightly pointed out that achieving market acceptance and foundry endorsement for a new simulator is a major challenge, and can be an insurmountable obstacle to success. On the other hand, having the optimizer wrapped around an existing commercial simulator means suffering huge performance penalties.
At Antrim, I had argued for the deeply embedded approach, so that we could build a revolutionary system that would be designed not so much for simulation as for optimization, by allowing the "synthesizer" to directly alter the matrix dynamically. Well, R&D would have none of that, and instead we ended up building the worst of both worlds. We had a new proprietary simulator AND, in order to accelerate that development as a stand-alone product, we still wrapped the optimizer around the outside.
For optimization, Ansyn's tool can potentially achieve higher performance than other solutions. They are also taking advantage of mutli-core processing, which has become popular for accelerating traditional SPICE simulators. I don't see any realization at this point to back up the provocative "synthesis" claim, but it will we interesting to see if Ansyn comes away from their 1st DAC visit with a desire to jump into the EDA fray, or stay local in the much smaller European market.
5. Follow-up Discussion with CoWare on modeling and simulation of next generation LTE modems
Following on my introduction to CoWare's LTE modem solution on Tuesday at DAC, I had the opportunity to sit down for a chat with Dr. Johannes Stahl, VP Marketing & Business Development. CoWare has addressed the concept of virtual platforms with a vertical market solution for the 4G mobile wireless market.
As a bit of background; the 4th generation (or 4G) of wireless technology will be characterized by a flat end-to-end internet protocol (IP) network that is optimized for broadband data communications. This is a very significant change as all preceding generations, including today's 3G, are based on (what is at best) a hybrid architecture that was optimized for voice from the outset. A partisan debate between advocates of two similar technologies for the radio access part of 4G networks, mobile WiMAX and LTE, has detracted from the development. As things stand today, mobile WiMAX has been deployed in several U.S. cities by Clearwire/Sprint, while LTE is yet to begin its first field trials. (For much more on this, see my report "The Emerging 4G Wireless Landscape in the U.S.").
With LTE being several years behind WiMAX in regards to SoC development and network deployment, a virtual platform to accelerate software and algorithm development is essential. At a Santa Clara Valley IEEE Communication Society meeting earlier this year, representatives of several WiMAX chip providers emphasized that the algorithms are the critical element to wireless performance, more thanthe silicon. Chip complexity is increasing, as RF front ends are integrated into single-chip SoCs to lower cost, size, and power.
CoWare was very effective in utilizing Twitter to publicize the LTE presentations in their booth:
CoWareAddressing the Design Challenges of ARM-based LTE Mobile Phone Designs Using System Virtualization 10:15am - 12:15pm, Booth 4359The ST-Ericsson "tweet" regarding the integration of a virtual platform with a tester was particularly interesting. My summary assessment is that it was refreshing to see a real application of Electronic System Level design, amongst all the blathering regarding ESL as the "next big thing" for EDA.
9:40 AM Jul 27th from web
ST-Ericsson talk starts at 11:00, using a Virtual Platform to Develop and Validate a UMTS Layer1 Protocol Software Stack 3665 #46DAC
10:23 AM Jul 27th from web
ST-Ericsson: Integrated ANITE wireless tester with Virtual Platform. Complete test bench created virtually. #3665 #46DAC
11:37 AM Jul 27th from web
Motorola: using SystemC simulation for product planning and architecture exploration of state-of-the art 2G/3G/LTE modem chipsets #46DAC
4:19 PM Jul 27th from web
6. PAVILION PANEL: The AMS Revival: Bipolar Thinking?
Chair: Dave Maliniak - Electronic Design, New York, NY
Panelists:
Christoph Grimm - Technische Univ. Wien, Vienna, Austria
Mike Woodward - The MathWorks, Inc., Natick, MA
David Smith - Synopsys, Inc., Hillsboro, OR
This panel produced my favorite quote at DAC, from David Smith: "AMS is the whole world!". Yes, The World Is Analog!
So, if you've followed my blogs for a while, you will know that it is a continuing source of annoyance to see how analog is treated by the "non-cognoscenti". At this year's DAC, we already had analog referred to as "stodgy" and now in need of a "revival" and "bipolar"? Very funny. We all know that only digital types can be truly bi-polar ;-)
The discussion here was intended as a forum on the application of higher-level AMS design languages, such as System-C/AMS. Hence no designers on the panel? I had to stifle a laugh when one of the panelists said that it is "up to management to convince designers" to use top down methodologies. Riiight... let me know how that goes for you.
The thing is, to the extent it exists, analog designers already work top-down. It's just that, like every aspect of analog design, it's hard for the non-cognoscenti to understand because it doesn't look like digital - and it never will. With Mathworks, the provider of MATLAB, on the panel that should have gone without saying. Designers often use MATLAB to do early, high-level architectural analysis. At companies that are large enough to staff CAD and library groups, AMS behavioral modeling is commonly used as well, in Verilog-AMS or VHDL-AMS.
As just about everyone knows, the biggest difference between analog and digital is that there is no automated algorithmic top-down analog synthesis - it's mostly manual. That is unlikely to change anytime soon. However, what the non-cognoscenti also forget or ignore, is that there is plenty of "bottom-up" design that has to occur in digital as well, before you can execute your synthesis flow. Those cell libraries don't just materialize out of nowhere.
Mixed-signal IP is also employed extensively in AMS SoCs, same as in digital. It's just that most analog specifications require tuning and optimization, which is - by the way - why the highest performance digital chips are custom as well.
One of the panelists stated the opinion that new tools & languages are not required, that all you need is methodology and management. Other panels, such as the one following this session, differed with that opinion. Speakers at the Tuesday morning AMS breakfast had already shown some of the limitations of currently available tools for AMS verification, which was correctly identified as the #1 problem in AMS design.
It would be valuable to extend some digital verification concepts to AMS, especially the concept of assertions. I was an early participant in the Accelera Requirements Definition Working Group, where we explored how Verilog-AMS and System Verilog might be integrated to address this need. I am concerned though, that these committees often end up focusing more on defining a language than on defining a solution to the real problems.
7. PANEL: Guess, Solder, Measure, Repeat – How Do I Get My Mixed-Signal Chip Right?
Chair: Ken Kundert - Designer’s Guide Consulting, Los Altos, CA
Panelists:
Georges Gielen - Katholieke Univ. Leuven, Leuven, Belgium
Martin O’Leary - Cadence Design Systems, Inc., San Jose, CA
Eric Grimme - Intel Corp., Hillsboro, OR
Sandeep Tare - Texas Instruments, Inc., Dallas, TX
Warren Wong - Synopsys, Inc., Mountain View, CA
I was happy to hear Prof. Gielen say that they still require their students to learn to solder and measure. Nobody should be granted a EE degree without ever actually building something.
No new ground was covered here, but as my final session at DAC it was a good wrapup on AMS issues.
- In a reversal of digital thinking, Intel described how they must now apply AMS verification to microprocessors. There are many analog phenomena to be accounted for, even in "purely" digital blocks; leakage, power-up/power-down, reliability, noise, variability, etc.
- TI presented some of the same material from the Tuesday AMS breakfast, discussing the complexity of verifying digitally-controlled analog blocks. Interface problems between multiple power domains, power-up/down transient behavior, and incomplete assumptions were some of the problems described.
- Eric from Intel said that they have not yet decided on the use of behavioral models, which require 10X the effort of digital modeling, versus Fast-SPICE. The current preference is for SPICE.
- Prof. Gielen talked about how using models is necessary, but risks leaving out details. He mentioned that academia is working on methods to aid in AMS model creation. Companies such as Lynguent and Orora were showing solutions in this space at DAC, but it is sad to see that we have not come further more than 10 years after we first started working on a solution at Antrim.
- In the Q&A, an engineer from Sony asked how often is AMS IP re-used? Intel said they re-use IP, but it still needs to be validated within the chip? TI also re-uses IP, but quite often it needs to be re-designed.
- Georges talked about how more designs are taking advantage of digital correction to be more resilient.
- In regards to noise & cross-talk: panelists stated that it just can't be simulated at the top level, and you need to rely on designer judgment.
- Intel would like to see analog assertion capability in System Verilog.
-Mike
Picking up from my Day 1 report, here are the highlights from my agenda on Day 2 (Tuesday, July 28th) at the 46th Design Automation Conference (DAC).
This summary is intended to just provide a glimpse of all the material that I have to digest. I will go into greater depth on the more interesting aspects as time permits.
Feel free to leave a comment to let me know the topics that you are most interested in reading more about.
Tuesday - Day 2
1. Synopsys' AMS Verification Breakfast
This annual event (which I organized and moderated last year), was setup this time to showcase customer experiences with HSPICE and the trio of Fast-SPICE simulators now being packaged under the "Custom Sim" label.
Panelists: Aaron Barker - Sun Microsystems, Eugene Chen - Altera, Sandeep Tare - Texas Instruments, Pier Luigi Daglio and Lyes Djama - ST Microelectronics
Presenter: Fu-Chieh Hsu - Vice President, Design and Technology Platform, Taiwan Semiconductor Manufacturing Company
After the Synopsys AMS Breakfast, I could only catch the last half of this presentation. That was somewhat unfortunate, as this was (in my opinion) the most significant event at the 46th DAC.
Fu-Chieh Hsu discussed the need to revolutionize the fabless semiconductor ecosystem, putting forth a proposal with TSMC's vision of a sustainable business model. Deeper collaboration is necessary at every level in the design chain to reduce redundant efforts and waste (a theme also heard later in the day at the Pavilion Panel Will Interoperable PDKs Fly in a Stodgy Analog World?).
The radical new business model that Fu-Chieh Hsu called for is community-based collaboration, with community investment to drive community ROI. The theme was "Collaborate to Innovate". At every level; from system to chip design to IP and packaging, and from EDA to foundry, the new business model requires "sharing the pains and glory". To aid in incubating fabless startups, deferral of upfront costs was proposed, to cultivate a "success-based" ecosystem similar to the IP business model but now extending to EDA and design services. In TSMC's view, this will be essential for future growth.
3. Presentation of ClioSoft SOS design management system
At the ClioSoft booth, I received a presentation of the SOS™ - Platform for Design Data Collaboration, which provides an integrated platform with a consistent interface for custom design implementation tools from Cadence, Mentor, Silicon Canvas and Synopsys. The ClioSoft tools can be used to bring discipline to the often ad hoc analog/custom design process through version control and the ability to record and restore the state of a design to past iterations. The need for such a tool becomes more important in light of Open Access interoperability, and the need for consistent data base management across tools sets.
4. IPL Lunch Workshop The EDA Earthquake: Interoperable PDKs Shakin’ Up the Analog Design World
Agenda:
Ron Burns spoke about using Open Access and iPDKS in their mixed Cadence/Synopsys environment. Interoperability is important at Wipro since their analog design team needs to be able to deliver IP that fits into customer's diverse environments. Ability to move IP from a Cadence to Synopsys environment is critical for Wipro. One shortcoming cited for the current Open Access database is the inability to store simulation states.
During the post-presentation Q&A, Chris Collins of Texas Instruments challenged the value of interoperable PDKs for IDMs like TI. He saw no need to move IP from one CAD environment to another, and asked whether there was any effort to establish interoperability at the foundry level. (A question that also came up later at the Pavilion Panel). The TSMC response was that older generation process nodes have very similar rule sets from the foundries, but that more state-of-the-art nanometer processes require tuning to a particular foundry.
5. Discussion with CoWare on modeling and simulation of next generation LTE modems
This was a meeting that would not have happened without Twitter. On Tuesday I already had three other items on my calendar at 2PM, but none of them appeared to be as interesting as this "tweet" from CoWare. Since I was totally booked the rest of the day, I changed my plans.
One of my areas of expertise (other than EDA), is in wireless communications - an industry that I have been covering more closely since my (involuntary) exit from Synopsys last year. I recently published an analysis of the U.S. wireless industry in The Emerging 4G Wireless Landscape in the U.S. Operators, Chip Sets, and Consumer Electronics. You can download a free excerpt at http://www.digdia.com.
So, making a connection between the EDA and Wireless industries during my visit to DAC suited me perfectly! FYI for CoWare's competitors in this space... sorry, didn't know you were there! Tweet.. tweet.
The folks at the CoWare booth were very helpful and well-informed (which, sadly, does not describe all DAC booth staff), chatting with me about the application of their tools for LTE development and introducing me to their VP of Marketing for a follow-up discussion the following day. Thanks guys!
6. Pavilion Panel: Will Interoperable PDKs Fly in a Stodgy Analog World?
Chair: Mike Santarini - Xilinx, Inc., San Jose, CA
Panelists: Ed Lechner - Synopsys, Bill Heiser - Cadence Design Systems, Tom Quan - Taiwan Semiconductor Manufacturing
This is my nominee for best Pavilion Panel at DAC, no contest! It had exactly the right representation for the topic. It may have been preferable to have a marketing representative from Cadence but Bill Heiser - a sales director - did a fine job.
Tom Quan from TMSC started the discussion by emphasizing the high (and increasing) level of effort that is required to create design kits for advanced processes. At 40nm and 28nm, the proximity effects are causing an explosion of context-sensitive parameters. The iPDKs will eventually reduce support costs for TSMC, though Mentor and Cadence PDKs will be maintained in the short term.
Cadence is now working with TSMC to see how their proprietary parameterized cells (pCells) can work with iPDKs. As Bill Heiser pointed out, the Cadence Virtuoso "front end" is still based on the proprietary SKILL language, and that is the basis of all the regression testing that they do.
Bill claimed that iPDKs offer a choice but not necessarily automation. The discussion got much more lively when Bill challenged Synopsys, saying that OA is about how to do integrated analog-digital design, so what about OA vs. MilkyWay (the proprietary Synopsys database for digital implementation)? Ed's response was that the Synopsys system supports data interchange and sharing between MilkyWay and OA.
Bill then challenged again, asking why openness for analog, but not for digital? He then went on to deflect the challenge to TSMC, asking Tom if TSMC would invite other foundries to share their iPDKs. In my opinion, this argument misses the point because it's all about interoperability of intellectual property, eliminating artificial barriers but not giving away IP. The PDK reveals nothing about how an EDA vendor's tools work. On the other hand, the design rules embodied in a PDK are tied very specifically to the manufacturer's process and each customer who receives the PDK is bound to protect that intellectual property. Tom's fitting retort to Bill: "are you in the business of subsidizing your competitor"?
Finally, Ed returned the challenge to Cadence, saying that he would welcome "with open arms" if Cadence would donate SKILL or a pCell evaluator to plug into the OA database.
All in all, a very lively discussion! As an added bonus if you have read this far, you can listen to it all here:
(I discovered this player does not work in Internet Explorer. Firefox preferred).
7. Conversation with Cambridge Analog Technologies about their high-speed/low-power ADCs
So... long before I worked in EDA, and even longer before I worked as an analyst of the wireless industry, I was a designer of high-speed analog-to-digital converters. It's been almost twenty years since I wrote it, but you can still buy my book on High Speed Analog-to-Digital Conversion on Amazon. Back in those days, I first met Cambridge Analog Technologies board member Charles Sodini at an ISSCC planning meeting. I then managed some research projects under Prof. Sodini's supervision at MIT which we funded from the GE Corporate R&D Labs. At that time, Cambridge CTO Harry Lee was a doctoral student at UC Berkeley, and our lab worked with him and other students to understand self-calibrating ADCs, and associated testing techniques to apply to the design work we were doing. Many people doubted that you could do analog in sub-1 micron back then, but look at where we are today.
8. Titan ADX: Take the Guesswork Out of Analog Design
Finally (such a long day, I had to skip the Denali party), I ended the 2nd day of DAC with a presentation on Magma's Titan ADX: Analog Design Accelerator. There was a noticeable increase in activity at this year's DAC associated with analog circuit optimization, which is the function of the ACX tool in Titan. (Along with AVP for virtual prototype - a physical placement, and ALX - a layout accelerator). This is a subject of interest to me going back to my time at Antrim Design Systems, where we had the crazy idea of developing analog synthesis. (We did make a lot of progress before the wheels fell off, and were awarded 5 patents - which now belong to Cadence).
Titan ACX is built from technology acquired from Mar Hershenson's Sabio Labs, which was itself a rebirth of the first attempt to commercialize this technology at Barcelona Design. Magma describes ACX as a tool that uses analog functional models built from process-independent equations to optimize blocks such as PLLs, bandgaps, and ADCs. The key difference from earlier positioning is that a user starts with an existing circuit, and then optimizes for a few objectives, such as area or power, and not to "synthesize" the entire circuit. That seems more reasonable, but the other constraint with this approach is that the circuit much match the model - which was a problem with the "geometric programming" methodology at Barcelona. It takes much longer to create and validate a new program of equations than to actually have an engineer design the circuit.
So, ACX would best be applied to analog block re-use and tuning. However, many circuits need to be re-architected to work at lower voltages in scaled processes, so at that point the model template and equations would need to be changed as well. That is a different skill than circuit design, which is why most attempts at analog synthesis have been limited to linear circuits that can be described algorithmically.
-----------------------------------------------------------------------------------------------------
Well, as I said after day 1... Phew!!
I still have Day 3 to compile, so stay tuned.
-Mike
This summary is intended to just provide a glimpse of all the material that I have to digest. I will go into greater depth on the more interesting aspects as time permits.
Feel free to leave a comment to let me know the topics that you are most interested in reading more about.
Tuesday - Day 2
1. Synopsys' AMS Verification Breakfast
This annual event (which I organized and moderated last year), was setup this time to showcase customer experiences with HSPICE and the trio of Fast-SPICE simulators now being packaged under the "Custom Sim" label.
Panelists: Aaron Barker - Sun Microsystems, Eugene Chen - Altera, Sandeep Tare - Texas Instruments, Pier Luigi Daglio and Lyes Djama - ST Microelectronics
- Aaron Barker from Sun emphasized the challenge of increased simulation model complexity due to proximity effects, and the need for simulation of statistical variation. He used table models with Monte Carlo analysis to speed up analysis, and called for the implementation of variability analysis in a Fast-SPICE tool.
- Eugene Chen from Altera talked the need to simulate 32 corners for process-related effects in 40nm processes with HSIM. Altera is evaluating the XA simulator and other "true SPICE" solutions for 28nm analysis. He also expressed a need to accelerate analyses that do not translate well to Fast-SPICE; including AC and S-parameter analysis. The 3-way collaboration of EDA-foundry-design house is essential for early access to advanced technology.
- Sandeep Tare from TI presented his hierarchical verification methodology, from analog IP building blocks to full SoC verification combining RTL and analog behavioral models. Automated methods of analog behavioral model equivalence checking is needed. Challenges include verifying programmable analog cores, power-up/power-down sequences, and multiple voltage domains. TI performs AMS co-simulation with System Verilog (SV), using a proprietary implementation of probing functions (e.g. $SNPS_GET_VOLT) that allow SV assertions to be used with SPICE simulation. Sandeep called for applying more digital verification techniques to mixed-signal designs, hoping that AMS formal verification may also be possible sometime in the future.
- Pier Luigi Daglio and Lyes Djama from ST Microelectronics presented their verification flow for RF/AMS SoCs with embedded Flash Memory. Functional verification, along with power-up/power-down sequences, and signal integrity analysis are essential. ST has employed XA, HSIM and the Waveview Analysis Command Environment (ACE) for automated regression testing. HSIMplus is used extensively for post-layout analysis. Co-simulation is performed with HSIM as the analog engine, linked to a "3rd party" digital simulator. The HSIMplus CircuitCheck option is being used, but ST is waiting for a "shareable" version of CircuitCheck that can be used with other simulators as well. One of the interesting observations from ST was that XA is currently the best simulator for SRAMs, replacing HSIM in this application.
Presenter: Fu-Chieh Hsu - Vice President, Design and Technology Platform, Taiwan Semiconductor Manufacturing Company
After the Synopsys AMS Breakfast, I could only catch the last half of this presentation. That was somewhat unfortunate, as this was (in my opinion) the most significant event at the 46th DAC.
Fu-Chieh Hsu discussed the need to revolutionize the fabless semiconductor ecosystem, putting forth a proposal with TSMC's vision of a sustainable business model. Deeper collaboration is necessary at every level in the design chain to reduce redundant efforts and waste (a theme also heard later in the day at the Pavilion Panel Will Interoperable PDKs Fly in a Stodgy Analog World?).
The radical new business model that Fu-Chieh Hsu called for is community-based collaboration, with community investment to drive community ROI. The theme was "Collaborate to Innovate". At every level; from system to chip design to IP and packaging, and from EDA to foundry, the new business model requires "sharing the pains and glory". To aid in incubating fabless startups, deferral of upfront costs was proposed, to cultivate a "success-based" ecosystem similar to the IP business model but now extending to EDA and design services. In TSMC's view, this will be essential for future growth.
3. Presentation of ClioSoft SOS design management system
At the ClioSoft booth, I received a presentation of the SOS™ - Platform for Design Data Collaboration, which provides an integrated platform with a consistent interface for custom design implementation tools from Cadence, Mentor, Silicon Canvas and Synopsys. The ClioSoft tools can be used to bring discipline to the often ad hoc analog/custom design process through version control and the ability to record and restore the state of a design to past iterations. The need for such a tool becomes more important in light of Open Access interoperability, and the need for consistent data base management across tools sets.
4. IPL Lunch Workshop The EDA Earthquake: Interoperable PDKs Shakin’ Up the Analog Design World
Agenda:
- Introduction & IPL overview and roadmap – Ed Lechner, Synopsys/IPL Alliance
- Interoperable PDK implementation – Neel Gopalan, Synopsys
- TSMC interoperable PDK – Steven Chen, TSMC
- Using an interoperable PDK in a multi-vendor flow– Ron Burns, Wipro
Ron Burns spoke about using Open Access and iPDKS in their mixed Cadence/Synopsys environment. Interoperability is important at Wipro since their analog design team needs to be able to deliver IP that fits into customer's diverse environments. Ability to move IP from a Cadence to Synopsys environment is critical for Wipro. One shortcoming cited for the current Open Access database is the inability to store simulation states.
During the post-presentation Q&A, Chris Collins of Texas Instruments challenged the value of interoperable PDKs for IDMs like TI. He saw no need to move IP from one CAD environment to another, and asked whether there was any effort to establish interoperability at the foundry level. (A question that also came up later at the Pavilion Panel). The TSMC response was that older generation process nodes have very similar rule sets from the foundries, but that more state-of-the-art nanometer processes require tuning to a particular foundry.
5. Discussion with CoWare on modeling and simulation of next generation LTE modems
This was a meeting that would not have happened without Twitter. On Tuesday I already had three other items on my calendar at 2PM, but none of them appeared to be as interesting as this "tweet" from CoWare. Since I was totally booked the rest of the day, I changed my plans.
#46DAC Modeling and simulation of next generation LTE modems booth #3665Now, for some of my "The World Is Analog" readers, you need to know that LTE does not mean "local truncation error" in this context. LTE is also an acronym for Long Term Evolution, an emerging 4th generation mobile wireless technology.
One of my areas of expertise (other than EDA), is in wireless communications - an industry that I have been covering more closely since my (involuntary) exit from Synopsys last year. I recently published an analysis of the U.S. wireless industry in The Emerging 4G Wireless Landscape in the U.S. Operators, Chip Sets, and Consumer Electronics. You can download a free excerpt at http://www.digdia.com.
So, making a connection between the EDA and Wireless industries during my visit to DAC suited me perfectly! FYI for CoWare's competitors in this space... sorry, didn't know you were there! Tweet.. tweet.
The folks at the CoWare booth were very helpful and well-informed (which, sadly, does not describe all DAC booth staff), chatting with me about the application of their tools for LTE development and introducing me to their VP of Marketing for a follow-up discussion the following day. Thanks guys!
6. Pavilion Panel: Will Interoperable PDKs Fly in a Stodgy Analog World?
Chair: Mike Santarini - Xilinx, Inc., San Jose, CA
Panelists: Ed Lechner - Synopsys, Bill Heiser - Cadence Design Systems, Tom Quan - Taiwan Semiconductor Manufacturing
This is my nominee for best Pavilion Panel at DAC, no contest! It had exactly the right representation for the topic. It may have been preferable to have a marketing representative from Cadence but Bill Heiser - a sales director - did a fine job.
Tom Quan from TMSC started the discussion by emphasizing the high (and increasing) level of effort that is required to create design kits for advanced processes. At 40nm and 28nm, the proximity effects are causing an explosion of context-sensitive parameters. The iPDKs will eventually reduce support costs for TSMC, though Mentor and Cadence PDKs will be maintained in the short term.
Cadence is now working with TSMC to see how their proprietary parameterized cells (pCells) can work with iPDKs. As Bill Heiser pointed out, the Cadence Virtuoso "front end" is still based on the proprietary SKILL language, and that is the basis of all the regression testing that they do.
Bill claimed that iPDKs offer a choice but not necessarily automation. The discussion got much more lively when Bill challenged Synopsys, saying that OA is about how to do integrated analog-digital design, so what about OA vs. MilkyWay (the proprietary Synopsys database for digital implementation)? Ed's response was that the Synopsys system supports data interchange and sharing between MilkyWay and OA.
Bill then challenged again, asking why openness for analog, but not for digital? He then went on to deflect the challenge to TSMC, asking Tom if TSMC would invite other foundries to share their iPDKs. In my opinion, this argument misses the point because it's all about interoperability of intellectual property, eliminating artificial barriers but not giving away IP. The PDK reveals nothing about how an EDA vendor's tools work. On the other hand, the design rules embodied in a PDK are tied very specifically to the manufacturer's process and each customer who receives the PDK is bound to protect that intellectual property. Tom's fitting retort to Bill: "are you in the business of subsidizing your competitor"?
Finally, Ed returned the challenge to Cadence, saying that he would welcome "with open arms" if Cadence would donate SKILL or a pCell evaluator to plug into the OA database.
All in all, a very lively discussion! As an added bonus if you have read this far, you can listen to it all here:
(I discovered this player does not work in Internet Explorer. Firefox preferred).
7. Conversation with Cambridge Analog Technologies about their high-speed/low-power ADCs
So... long before I worked in EDA, and even longer before I worked as an analyst of the wireless industry, I was a designer of high-speed analog-to-digital converters. It's been almost twenty years since I wrote it, but you can still buy my book on High Speed Analog-to-Digital Conversion on Amazon. Back in those days, I first met Cambridge Analog Technologies board member Charles Sodini at an ISSCC planning meeting. I then managed some research projects under Prof. Sodini's supervision at MIT which we funded from the GE Corporate R&D Labs. At that time, Cambridge CTO Harry Lee was a doctoral student at UC Berkeley, and our lab worked with him and other students to understand self-calibrating ADCs, and associated testing techniques to apply to the design work we were doing. Many people doubted that you could do analog in sub-1 micron back then, but look at where we are today.
8. Titan ADX: Take the Guesswork Out of Analog Design
Finally (such a long day, I had to skip the Denali party), I ended the 2nd day of DAC with a presentation on Magma's Titan ADX: Analog Design Accelerator. There was a noticeable increase in activity at this year's DAC associated with analog circuit optimization, which is the function of the ACX tool in Titan. (Along with AVP for virtual prototype - a physical placement, and ALX - a layout accelerator). This is a subject of interest to me going back to my time at Antrim Design Systems, where we had the crazy idea of developing analog synthesis. (We did make a lot of progress before the wheels fell off, and were awarded 5 patents - which now belong to Cadence).
Titan ACX is built from technology acquired from Mar Hershenson's Sabio Labs, which was itself a rebirth of the first attempt to commercialize this technology at Barcelona Design. Magma describes ACX as a tool that uses analog functional models built from process-independent equations to optimize blocks such as PLLs, bandgaps, and ADCs. The key difference from earlier positioning is that a user starts with an existing circuit, and then optimizes for a few objectives, such as area or power, and not to "synthesize" the entire circuit. That seems more reasonable, but the other constraint with this approach is that the circuit much match the model - which was a problem with the "geometric programming" methodology at Barcelona. It takes much longer to create and validate a new program of equations than to actually have an engineer design the circuit.
So, ACX would best be applied to analog block re-use and tuning. However, many circuits need to be re-architected to work at lower voltages in scaled processes, so at that point the model template and equations would need to be changed as well. That is a different skill than circuit design, which is why most attempts at analog synthesis have been limited to linear circuits that can be described algorithmically.
-----------------------------------------------------------------------------------------------------
Well, as I said after day 1... Phew!!
I still have Day 3 to compile, so stay tuned.
-Mike
I think this was my 15th Design Automation Conference (DAC), but the very 1st which I attended as an observer and not as an employee of an exhibitor company. That made it a very different experience, giving me the opportunity to partake in a much broader view of the Electronic Design Automation (EDA) industry, one that is more fitting with my current role as a technology industry analyst. Most EDA veterans will probably agree with me when I say that I really enjoyed not being tied to a booth or demo suite this time.
If you are not familiar with EDA, simply put it is an industry group which provides tools that semiconductor company engineers use to design their chips. EDA is a key component of the semiconductor ecosystem, which IBM's Dr. Juan-Antonio Carballo referred to as the "parent industry" while moderating the annual CEO panel discussion. EDA also provides tools for the before and after of IC design; for electronic system-level (ESL) architectural design and for printed-circuit board (PCB) design. There is an ongoing emphasis on moving EDA further up the chain to system level, as chip complexity increases and the core IC tools have become commoditized. For my readers who have followed my posts on the wireless industry, EDA system level tools are playing an increasingly important role in development of 4G technology.
Though many within EDA have attempted to describe an "EDA ecosystem", the true role of EDA as a supplier to the much larger electronics industry was never more evident than at the 46th Design Automation Conference. More on that later.
The official "preliminary" DAC attendee count came in at 3,247 "exhibit only", a 12% increase from last year, no doubt due to the move back to San Francisco after trips through Anaheim (2008) and San Diego (2007). That count includes the press, analysts and employees of approximately 200 exhibitor companies. The crowd seemed light in the Moscone Center, but my schedule was so full that I didn't get to see some of the companies I wanted to visit during my three days. I came away with a lot of information to process and report on, so a quick summary debrief is probably the best way to start.
Herein then are the highlights from my agenda. I will go into greater depth on the more interesting aspects as time permits. Hopefully, the breadth of this summary will provide a glimpse into just how much information there is to digest. (This post got so long that I split it up into Day 1 - Day 3).
Feel free to leave a comment on areas that you are most interested in.
Monday - Day 1
1. Gary Smith's pavilion presentation on "Trends and What’s Hot at DAC"
Gary Smith has been known as "the EDA analyst" for many years, and he traditionally kicks off DAC with his "What to See" presentation. He now works for the DAC organizers as a member of the DAC Strategy Committee, which may explain his (ineffective) attempt to lead a chant of "I Love DAC" at the beginning of the Monday morning session. It was uncomfortable to see an industry analyst acting as an industry cheerleader.
As in recent years, Gary emphasized ESL, ESL, and ESL. I counted 16 ESL companies on his "What To See" list, out of a total of 24. Indeed, the need for advances in System on a Chip (SoC) design flows was a recurring theme at the show.
2. TSMC Open Innovation Platform Theater
Open Innovation is a major push from TSMC, showing that the days of proprietary formats for EDA tools may finally be coming to an end in the foundry design flows. The TSMC booth was a convenient place to stop and get a quick presentation from members of the TSMC Open Innovation Forum.
3. Jim Hogan's panel of "Hogan’s Heroes: The Long Road to System-Level Sign-Off"
Jim's panel included Grant Pierce, CEO of Sonics, Steve Leibson - Technology and Marketing Consultant, Peter Levin - Dept. of Veterans Affairs (former CEO of DAFCA). Continuing the ESL theme, Jim highlighted how SoCs are more difficult than ever to design because of the "big change" to heterogeneous multiprocessor architectures.
Panelist comments:
Panelists were; Jim Hogan - EDA angel investor and industry mover and shaker, Mike Fazeli - Atrenta VP of Strategic Development, and Bernard Murphy - CTO at Atrenta.
This was an interesting new experiment by Atrenta, which recognized the rising importance of bloggers in the EDA industry. It was almost a continuation of Jim Hogan's panel in a more intimate setting, coming immediately after the pavilion panel discussion. Other participants included Paul McLellan of EDA Graffiti.
Some of the discussion points:
Moderated by Dr. Juan-Antonio Carballo. Panelists: Aart de Geus - Synopsys, Walden C. Rhines - Mentor Graphics, Lip-Bu Tan - Cadence Design Systems.
I will have more to say about this session, which lasted more than 1:15, but here are a few bullets.
-Mike
If you are not familiar with EDA, simply put it is an industry group which provides tools that semiconductor company engineers use to design their chips. EDA is a key component of the semiconductor ecosystem, which IBM's Dr. Juan-Antonio Carballo referred to as the "parent industry" while moderating the annual CEO panel discussion. EDA also provides tools for the before and after of IC design; for electronic system-level (ESL) architectural design and for printed-circuit board (PCB) design. There is an ongoing emphasis on moving EDA further up the chain to system level, as chip complexity increases and the core IC tools have become commoditized. For my readers who have followed my posts on the wireless industry, EDA system level tools are playing an increasingly important role in development of 4G technology.
Though many within EDA have attempted to describe an "EDA ecosystem", the true role of EDA as a supplier to the much larger electronics industry was never more evident than at the 46th Design Automation Conference. More on that later.
The official "preliminary" DAC attendee count came in at 3,247 "exhibit only", a 12% increase from last year, no doubt due to the move back to San Francisco after trips through Anaheim (2008) and San Diego (2007). That count includes the press, analysts and employees of approximately 200 exhibitor companies. The crowd seemed light in the Moscone Center, but my schedule was so full that I didn't get to see some of the companies I wanted to visit during my three days. I came away with a lot of information to process and report on, so a quick summary debrief is probably the best way to start.
Herein then are the highlights from my agenda. I will go into greater depth on the more interesting aspects as time permits. Hopefully, the breadth of this summary will provide a glimpse into just how much information there is to digest. (This post got so long that I split it up into Day 1 - Day 3).
Feel free to leave a comment on areas that you are most interested in.
Monday - Day 1
1. Gary Smith's pavilion presentation on "Trends and What’s Hot at DAC"
Gary Smith has been known as "the EDA analyst" for many years, and he traditionally kicks off DAC with his "What to See" presentation. He now works for the DAC organizers as a member of the DAC Strategy Committee, which may explain his (ineffective) attempt to lead a chant of "I Love DAC" at the beginning of the Monday morning session. It was uncomfortable to see an industry analyst acting as an industry cheerleader.
As in recent years, Gary emphasized ESL, ESL, and ESL. I counted 16 ESL companies on his "What To See" list, out of a total of 24. Indeed, the need for advances in System on a Chip (SoC) design flows was a recurring theme at the show.
2. TSMC Open Innovation Platform Theater
Open Innovation is a major push from TSMC, showing that the days of proprietary formats for EDA tools may finally be coming to an end in the foundry design flows. The TSMC booth was a convenient place to stop and get a quick presentation from members of the TSMC Open Innovation Forum.
3. Jim Hogan's panel of "Hogan’s Heroes: The Long Road to System-Level Sign-Off"
Jim's panel included Grant Pierce, CEO of Sonics, Steve Leibson - Technology and Marketing Consultant, Peter Levin - Dept. of Veterans Affairs (former CEO of DAFCA). Continuing the ESL theme, Jim highlighted how SoCs are more difficult than ever to design because of the "big change" to heterogeneous multiprocessor architectures.
Panelist comments:
- Need integrated communication standards. Must be driven by smaller companies.
- Standards needed, at the "right" level of abstraction.
- How can we "capture the application"?
- What about reliability? Reliability definition depends on willingness to pay.
- 'C'-language models lack timing information, and can't detect manufacturing faults.
- Variability becomes more of an issue, which system design tools currently don't handle.
- Virtual platforms are of increasing importance. Must develop software with the possibility of multiple hardware implementations.
- No one company can do it, need a "virtual" corporation".
- How to make money in ESL?
Panelists were; Jim Hogan - EDA angel investor and industry mover and shaker, Mike Fazeli - Atrenta VP of Strategic Development, and Bernard Murphy - CTO at Atrenta.
This was an interesting new experiment by Atrenta, which recognized the rising importance of bloggers in the EDA industry. It was almost a continuation of Jim Hogan's panel in a more intimate setting, coming immediately after the pavilion panel discussion. Other participants included Paul McLellan of EDA Graffiti.
Some of the discussion points:
- SoC design is now about optimization, not features.
- Verification requires building quality in.
- Time-to-market delays and yield issues are increasing at sub-40nm process nodes, affecting time to ROI.
- More on collaboration needed; partnering of system and consumer product companies such as Apple and ARM.
- "It's not an EDA problem, it's a semiconductor problem"
- Some companies, such as Cisco, have moved to FPGAs in systems that provide margin, "software in-a-box". This requires same tools as SoC.
- Prediction for 2 DACs from now: "IP explodes", more verification required, IDMs divest.
- Changing EDA-Semiconductor relationship
Moderated by Dr. Juan-Antonio Carballo. Panelists: Aart de Geus - Synopsys, Walden C. Rhines - Mentor Graphics, Lip-Bu Tan - Cadence Design Systems.
I will have more to say about this session, which lasted more than 1:15, but here are a few bullets.
- Wally: Effect of economic downturn on EDA: 1st year of "negative growth". (Hmm.. I wonder if that describes the auto industry.. negative growth? Oh how I miss George Carlin!).
- Aart: the entire industry has to be about increase in efficiency. The entire global standard of living has lowered.
- Facing a "massive squeeze".
- What are EDA CEOs looking for? Overall cost of design is an endemic issue. What can change time-to-market? Cost of system design - need a holistic view.
- What about innovation? Investment in fabless companies is down 70%. Startups must emphasize capital efficiency, $12M per tapeout.
- What about EDA startups? Advice to address hard problems, such as system abstraction. EDA core is a mature market. Design-for-manufacturing (DFM), ESL and analog provide growth.
- An incremental philosophy has taken over in startups, reduction in hi-tech risk taking. Too many companies want increments, but are unwilling to pay for new features.
- Aart: Customer consolidation is a problem for EDA vendors; attrition and bankruptcies. Predicts we will see more later this year.
- Should EDA have a larger share of semiconductor revenues? Aart: That is a "BS" question! Must have an economic push.
- Are IP and services growing? Synopsys has increased investment in IP. There is increasing outsourcing to physical layout services.
- Could EDA move into other industries? Wally: Medical, military, and aerospace. Home power management.
- Are you running your company differently? Aart: Do whatever we can to help customers survive.
- Aart: Need more EDA talent to see multiple aspects of a problem, how to make a design flow work together. Need to grow that talent. Great opportunity.
-Mike
