This summary is intended to just provide a glimpse of all the material that I have to digest. I will go into greater depth on the more interesting aspects as time permits.
Feel free to leave a comment to let me know the topics that you are most interested in reading more about.
Tuesday - Day 2
1. Synopsys' AMS Verification Breakfast
This annual event (which I organized and moderated last year), was setup this time to showcase customer experiences with HSPICE and the trio of Fast-SPICE simulators now being packaged under the "Custom Sim" label.
Panelists: Aaron Barker - Sun Microsystems, Eugene Chen - Altera, Sandeep Tare - Texas Instruments, Pier Luigi Daglio and Lyes Djama - ST Microelectronics
- Aaron Barker from Sun emphasized the challenge of increased simulation model complexity due to proximity effects, and the need for simulation of statistical variation. He used table models with Monte Carlo analysis to speed up analysis, and called for the implementation of variability analysis in a Fast-SPICE tool.
- Eugene Chen from Altera talked the need to simulate 32 corners for process-related effects in 40nm processes with HSIM. Altera is evaluating the XA simulator and other "true SPICE" solutions for 28nm analysis. He also expressed a need to accelerate analyses that do not translate well to Fast-SPICE; including AC and S-parameter analysis. The 3-way collaboration of EDA-foundry-design house is essential for early access to advanced technology.
- Sandeep Tare from TI presented his hierarchical verification methodology, from analog IP building blocks to full SoC verification combining RTL and analog behavioral models. Automated methods of analog behavioral model equivalence checking is needed. Challenges include verifying programmable analog cores, power-up/power-down sequences, and multiple voltage domains. TI performs AMS co-simulation with System Verilog (SV), using a proprietary implementation of probing functions (e.g. $SNPS_GET_VOLT) that allow SV assertions to be used with SPICE simulation. Sandeep called for applying more digital verification techniques to mixed-signal designs, hoping that AMS formal verification may also be possible sometime in the future.
- Pier Luigi Daglio and Lyes Djama from ST Microelectronics presented their verification flow for RF/AMS SoCs with embedded Flash Memory. Functional verification, along with power-up/power-down sequences, and signal integrity analysis are essential. ST has employed XA, HSIM and the Waveview Analysis Command Environment (ACE) for automated regression testing. HSIMplus is used extensively for post-layout analysis. Co-simulation is performed with HSIM as the analog engine, linked to a "3rd party" digital simulator. The HSIMplus CircuitCheck option is being used, but ST is waiting for a "shareable" version of CircuitCheck that can be used with other simulators as well. One of the interesting observations from ST was that XA is currently the best simulator for SRAMs, replacing HSIM in this application.
Presenter: Fu-Chieh Hsu - Vice President, Design and Technology Platform, Taiwan Semiconductor Manufacturing Company
After the Synopsys AMS Breakfast, I could only catch the last half of this presentation. That was somewhat unfortunate, as this was (in my opinion) the most significant event at the 46th DAC.
Fu-Chieh Hsu discussed the need to revolutionize the fabless semiconductor ecosystem, putting forth a proposal with TSMC's vision of a sustainable business model. Deeper collaboration is necessary at every level in the design chain to reduce redundant efforts and waste (a theme also heard later in the day at the Pavilion Panel Will Interoperable PDKs Fly in a Stodgy Analog World?).
The radical new business model that Fu-Chieh Hsu called for is community-based collaboration, with community investment to drive community ROI. The theme was "Collaborate to Innovate". At every level; from system to chip design to IP and packaging, and from EDA to foundry, the new business model requires "sharing the pains and glory". To aid in incubating fabless startups, deferral of upfront costs was proposed, to cultivate a "success-based" ecosystem similar to the IP business model but now extending to EDA and design services. In TSMC's view, this will be essential for future growth.
3. Presentation of ClioSoft SOS design management system
At the ClioSoft booth, I received a presentation of the SOS™ - Platform for Design Data Collaboration, which provides an integrated platform with a consistent interface for custom design implementation tools from Cadence, Mentor, Silicon Canvas and Synopsys. The ClioSoft tools can be used to bring discipline to the often ad hoc analog/custom design process through version control and the ability to record and restore the state of a design to past iterations. The need for such a tool becomes more important in light of Open Access interoperability, and the need for consistent data base management across tools sets.
4. IPL Lunch Workshop The EDA Earthquake: Interoperable PDKs Shakin’ Up the Analog Design World
- Introduction & IPL overview and roadmap – Ed Lechner, Synopsys/IPL Alliance
- Interoperable PDK implementation – Neel Gopalan, Synopsys
- TSMC interoperable PDK – Steven Chen, TSMC
- Using an interoperable PDK in a multi-vendor flow– Ron Burns, Wipro
Ron Burns spoke about using Open Access and iPDKS in their mixed Cadence/Synopsys environment. Interoperability is important at Wipro since their analog design team needs to be able to deliver IP that fits into customer's diverse environments. Ability to move IP from a Cadence to Synopsys environment is critical for Wipro. One shortcoming cited for the current Open Access database is the inability to store simulation states.
During the post-presentation Q&A, Chris Collins of Texas Instruments challenged the value of interoperable PDKs for IDMs like TI. He saw no need to move IP from one CAD environment to another, and asked whether there was any effort to establish interoperability at the foundry level. (A question that also came up later at the Pavilion Panel). The TSMC response was that older generation process nodes have very similar rule sets from the foundries, but that more state-of-the-art nanometer processes require tuning to a particular foundry.
5. Discussion with CoWare on modeling and simulation of next generation LTE modems
This was a meeting that would not have happened without Twitter. On Tuesday I already had three other items on my calendar at 2PM, but none of them appeared to be as interesting as this "tweet" from CoWare. Since I was totally booked the rest of the day, I changed my plans.
#46DAC Modeling and simulation of next generation LTE modems booth #3665Now, for some of my "The World Is Analog" readers, you need to know that LTE does not mean "local truncation error" in this context. LTE is also an acronym for Long Term Evolution, an emerging 4th generation mobile wireless technology.
One of my areas of expertise (other than EDA), is in wireless communications - an industry that I have been covering more closely since my (involuntary) exit from Synopsys last year. I recently published an analysis of the U.S. wireless industry in The Emerging 4G Wireless Landscape in the U.S. Operators, Chip Sets, and Consumer Electronics. You can download a free excerpt at http://www.digdia.com.
So, making a connection between the EDA and Wireless industries during my visit to DAC suited me perfectly! FYI for CoWare's competitors in this space... sorry, didn't know you were there! Tweet.. tweet.
The folks at the CoWare booth were very helpful and well-informed (which, sadly, does not describe all DAC booth staff), chatting with me about the application of their tools for LTE development and introducing me to their VP of Marketing for a follow-up discussion the following day. Thanks guys!
6. Pavilion Panel: Will Interoperable PDKs Fly in a Stodgy Analog World?
Chair: Mike Santarini - Xilinx, Inc., San Jose, CA
Panelists: Ed Lechner - Synopsys, Bill Heiser - Cadence Design Systems, Tom Quan - Taiwan Semiconductor Manufacturing
This is my nominee for best Pavilion Panel at DAC, no contest! It had exactly the right representation for the topic. It may have been preferable to have a marketing representative from Cadence but Bill Heiser - a sales director - did a fine job.
Tom Quan from TMSC started the discussion by emphasizing the high (and increasing) level of effort that is required to create design kits for advanced processes. At 40nm and 28nm, the proximity effects are causing an explosion of context-sensitive parameters. The iPDKs will eventually reduce support costs for TSMC, though Mentor and Cadence PDKs will be maintained in the short term.
Cadence is now working with TSMC to see how their proprietary parameterized cells (pCells) can work with iPDKs. As Bill Heiser pointed out, the Cadence Virtuoso "front end" is still based on the proprietary SKILL language, and that is the basis of all the regression testing that they do.
Bill claimed that iPDKs offer a choice but not necessarily automation. The discussion got much more lively when Bill challenged Synopsys, saying that OA is about how to do integrated analog-digital design, so what about OA vs. MilkyWay (the proprietary Synopsys database for digital implementation)? Ed's response was that the Synopsys system supports data interchange and sharing between MilkyWay and OA.
Bill then challenged again, asking why openness for analog, but not for digital? He then went on to deflect the challenge to TSMC, asking Tom if TSMC would invite other foundries to share their iPDKs. In my opinion, this argument misses the point because it's all about interoperability of intellectual property, eliminating artificial barriers but not giving away IP. The PDK reveals nothing about how an EDA vendor's tools work. On the other hand, the design rules embodied in a PDK are tied very specifically to the manufacturer's process and each customer who receives the PDK is bound to protect that intellectual property. Tom's fitting retort to Bill: "are you in the business of subsidizing your competitor"?
Finally, Ed returned the challenge to Cadence, saying that he would welcome "with open arms" if Cadence would donate SKILL or a pCell evaluator to plug into the OA database.
All in all, a very lively discussion! As an added bonus if you have read this far, you can listen to it all here:
(I discovered this player does not work in Internet Explorer. Firefox preferred).
7. Conversation with Cambridge Analog Technologies about their high-speed/low-power ADCs
So... long before I worked in EDA, and even longer before I worked as an analyst of the wireless industry, I was a designer of high-speed analog-to-digital converters. It's been almost twenty years since I wrote it, but you can still buy my book on High Speed Analog-to-Digital Conversion on Amazon. Back in those days, I first met Cambridge Analog Technologies board member Charles Sodini at an ISSCC planning meeting. I then managed some research projects under Prof. Sodini's supervision at MIT which we funded from the GE Corporate R&D Labs. At that time, Cambridge CTO Harry Lee was a doctoral student at UC Berkeley, and our lab worked with him and other students to understand self-calibrating ADCs, and associated testing techniques to apply to the design work we were doing. Many people doubted that you could do analog in sub-1 micron back then, but look at where we are today.
8. Titan ADX: Take the Guesswork Out of Analog Design
Finally (such a long day, I had to skip the Denali party), I ended the 2nd day of DAC with a presentation on Magma's Titan ADX: Analog Design Accelerator. There was a noticeable increase in activity at this year's DAC associated with analog circuit optimization, which is the function of the ACX tool in Titan. (Along with AVP for virtual prototype - a physical placement, and ALX - a layout accelerator). This is a subject of interest to me going back to my time at Antrim Design Systems, where we had the crazy idea of developing analog synthesis. (We did make a lot of progress before the wheels fell off, and were awarded 5 patents - which now belong to Cadence).
Titan ACX is built from technology acquired from Mar Hershenson's Sabio Labs, which was itself a rebirth of the first attempt to commercialize this technology at Barcelona Design. Magma describes ACX as a tool that uses analog functional models built from process-independent equations to optimize blocks such as PLLs, bandgaps, and ADCs. The key difference from earlier positioning is that a user starts with an existing circuit, and then optimizes for a few objectives, such as area or power, and not to "synthesize" the entire circuit. That seems more reasonable, but the other constraint with this approach is that the circuit much match the model - which was a problem with the "geometric programming" methodology at Barcelona. It takes much longer to create and validate a new program of equations than to actually have an engineer design the circuit.
So, ACX would best be applied to analog block re-use and tuning. However, many circuits need to be re-architected to work at lower voltages in scaled processes, so at that point the model template and equations would need to be changed as well. That is a different skill than circuit design, which is why most attempts at analog synthesis have been limited to linear circuits that can be described algorithmically.
Well, as I said after day 1... Phew!!
I still have Day 3 to compile, so stay tuned.