With the EDA sector still struggling to pull out of a six-quarter long decline in revenue, the ICCAD organizers broke from the academic theme in a session titled "What EDA Needs to Change for 2020 Success" - presented by industry veterans Jim Hogan and Paul McLellan, where industry analysts, bloggers and journalists were invited to participate.
Some of the topics put forth for discussion were:
- What will be the silicon platform for complex chip design in the next decade?
- Software signoff why do we need it?.....or do we?
- Where is the highest value area for EDA vendors given the requirements of the electronic systems designer and platform provider?
In my opinion, repeating the same EDA paradigm at yet another level is no solution for industry growth. At best, it can only help recover some of the lost revenue that will continue to result from pervasive commoditization of older generation tools. Where's the innovation?
EDA has for far too long reflected upon the success of logic synthesis, perhaps the last true innovation in design methodology, and searched in vain for a repeat performance - i.e. ESL or electronic system-level design. The real problem with this idea revealed itself only towards the closing part of the Q&A, in a perhaps rhetorical question: "how many EDA companies can handle total SoC integration?" The answer is none.
This is not to be taken entirely as a criticism of EDA. Only a company that actually does SoC design, such as Intel or Texas Instruments, is capable of developing comprehensive knowledge of the entire process. I have written before of the need for greater collaboration between EDA and semiconductor companies. However, EDA has made the problem worse by developing fragmented views developed within point tool silos, exacerbated by artificial barriers. There have been no shortage of abstraction levels developed for use in IC design flows. What is lacking is the 3rd axis for the chart above - the links across abstraction levels to connect the hierarchical SoC design process.
Here's one example. When the introduction of hardware-description languages (HDLs) enabled replacement of transistor-level simulation for logic, it took years to build links between the two levels of abstraction such as the IEEE 1364 Verilog PLI. Yet to this day, some vendors refuse to support VPI, offering only proprietary interfaces in an attempt to lock users into a single company's products.
There are numerous other examples where abstraction levels are, at best, poorly linked:
- separate (and proprietary) physical databases for analog and digital flows
- no closed loop between SPICE and analog behavioral abstraction, such as Verilog-A or MATLAB
- lack of connection between design verification and ATE
We can see the problems in 2020 if we just look closer at the problems at hand today. Without breaking down barriers in the flow, in ten years they only get worse.