- Validating WiMAX OFDMA Using SystemVerilog and VMM
- Albert Chiang, Wei-Hua Han, Synopsys, inc.
- Bhanu Kapoor of Mimasic
- Shyam Rapaka, Tapan Halder
- Verification Group, Synopsys Inc.
- Vikas Chandra ARM R&D
- Dr. Greg Tumbush
- Tumbush Enterprises
- William Gonnason, Dustin Griesdorf , Alaa El-agha, Gareth Weale, Marc Matthey, Andreas Drollinger
- ON Semiconductor
- Holger Meiners
The subject of the last paper in the Mixed-Signal Design and Verification session at DVCon was a methodology for RF/mixed-signal ASICs that was applied to a hearing aid design. The critical goal of the methodology was shortening the design cycle by developing a complete “executable specification” in System-C that could link to the RF/analog simulations that were performed with Agilent’s Advanced Design System (ADS).
For the RF/analog portion of the design, nothing new was introduced beyond a standard application of ADS. However, by adopting System-C for the digital subsystem, the overall level of abstraction was moved up in the design hierarchy such that a complete (executable) architectural model could be constructed. This was contrasted with what the author’s referred to as a “traditional” design flow, where executable models did not exist until the block-level design phase consisting of VHDL/Verilog and analog schematics.
ADS provides the circuit to architectural behavioral modeling capability for the RF subsystem, along with support for co-simulation with System-C. That capability allowed architectural tradeoffs to be made in RF front-end, resulting in a model that then served as the testbench for the digital subsystem.
Focusing on the AMS side of this RF/mixed-signal design methodology, it is significant to note the number of manual steps that still exist in the verification methodology compared to the digital flow. These are the holes that the EDA industry must address to make AMS verification as robust as digital. For example, the authors stated that the “RF front-end model was refined based on feedback from the circuit designers”. This is not the first time I have heard of the lack of automated circuit-behavioral model-checking. It takes an experienced team of modeling engineers and designers can pull this off, but the process is still error prone.
Another factor limiting RF/AMS model checking is simulator performance. The authors noted that “the VCO noise cannot be simulated in the Cadence environment because of the length of simulation time required”. It is unknown whether any attempt was made to employ a “analog Fast-SPICE” simulator to overcome this obstacle. As is always the case, the choice of abstraction level came down to a tradeoff “between confidence level in the model and simulation speed”.
In the full-chip simulation, only digital Verilog models of basic analog behavior were used for critical functions. Again, the “correctness” of each model relied on signoff by the analog designer in charge of that component.