AMS Verification at DVCon – Part I

This year's DVCon session on Mixed-Signal Design and Verification included three presentations:

• Validating WiMAX OFDMA Using SystemVerilog and VMM
  
  • Albert Chiang, Wei-Hua Han
    
    • Synopsys, Inc.
      
  • Bhanu Kapoor of Mimasic
    
• A SystemVerilog Approach for Analog/Mixed-Signal Verification
  
  • Shyam Rapaka, Tapan Halder
    
    • Verification Group, Synopsys Inc.
      
  • Vikas Chandra ARM R&D
    
• Get to ASICs Faster - A Novel Mixed Signal Design Methodology
  
  • Dr. Greg Tumbush
    
    • Tumbush Enterprises
      
  • William Gonnason, Dustin Griesdorf , Alaa El-agha, Gareth Weale, Marc Matthey, Andreas Drollinger
    
    • ON Semiconductor
      
  • Holger Meiners
    
    • holger_meiners@yahoo.de
      

Paper #1

The first paper on "Validating WiMAX" was presented by Synopsys, with a focus on features of System Verilog rather than describing a complete verification methodology for WiMAX transceivers. At the recent International Solid State Circuits Conference, several WiMAX designs were presented for fully integrated single-chip SoC designs in RF-CMOS (see Highlights of ISSCC 2009). The complex RF and analog portions of these designs require rigorous verification at the transistor level. While the authors make brief mention of this in the text of the paper, saying:

"… it is important to ensure that the design is simulated not only at the individual block-level but making use of a high capacity, transistor-level simulation engine to simulate the entire design including all post-layout parasitics that can have a detrimental effect on the front-end performance."

no mention of how this was performed was included in the talk.

In verifying the complete design of RF-AMS SoCs, the major challenge is how to verify the analog-digital interface to ensure correct functional behavior for the entire SoC. It is unfortunate that, while this paper was part of the "Mixed-Signal Design and Verification " session at DVCon, the presentation was completely focused on a digital functional verification problem. SystemVerilog classes were applied to model WiMAX frames, consisting of "zones" and "bursts" of data from the OFDMA transmission, in order to make use of constrained randomization techniques.

It appears that the authors of this paper employed a "divide & conquer" verification strategy, with separation of analog and digital into their own domains. A brief mention is made at the end of the paper, regarding use of Verilog-AMS to model the behavior of the RF front-end. The example of a VCO model is strictly Verilog-A however, with no digital co-simulation or connection to mixed-signal blocks. Such an approach could be error-prone, as it is dangerous to assume that the proper digital symbols were received or transmitted in the RF-AMS front end.

-Mike